DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to Applicant’s Amendment filed on 12/24/2025.
Claims 1 and 3-14 are presented for examination. Claims 1 and 3 have been amended. Claims 11-14 have been added. Claim 2 has been cancelled.
Applicant’s amendments to the drawings and claims have overcome drawing objection and 112 rejections set forth in the non-Final Office Action mailed 9/24/2025.
Examiner Notes
Examiner cites particular columns, paragraphs, figures and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirely as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Claim Objections
Claims 1 and 3-14 are objected to because of the following informalities:
“the quantity of resource” at last 3rd line of claim 1 should be: the quantity of resource used by each operator in each of the second data processing models.
“scheduling sequence, and parallel execution state” at last 3rd line to last 2nd line of claim 1 should be: the scheduling sequence and the parallel execution state.
Claims 3-8 and 11-14 are object for failing to cure the deficiency from their respective parent claim by dependency.
“the quantity of resource used by each operator” of last two lines of claim 3 should be: the quantity of resource used by each operator in each of the first data processing model.
“between operators in the second data processing models” of claim 13 should be: between one or more parallel-executed operators in each of the second data processing models
“performing performance testing on the operators” of claim 13 should be: performing performance testing on the one or more parallel-executed operators.
“between parallel-executed operators” of claim 13 should be: between each of the one or more parallel-executed operators.
“between two operators” of claim 13 should be: between each of the one or more parallel-executed operators.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 11 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding to Claim 11, the limitation “executing the integrated operator in a pipelined parallel manner confirming to the parallel execution state” (emphasis added) at last two lines fails to comply with the written description requirement. First of all, such feature is a new limitation/feature that does not presented at original claims submitted at 7/1/2024.
Secondly, according to the context of claim 11, claimed “integrated operator” is defined as merging or fusing several consecutive operators in the first data processing models. According to claim 1 (claim 11 depends on claim 3 and claim 3 depends on claim 1), the claimed “parallel execution state” is defined as “for each operator in each of the second data processing models”. In this way, the claimed executing limitation mentioned above requires executing the integrated operator formed by operators from the first data processing models to confirm the parallel execution state associated with operators from the second data processing models. Examiner did not find out any description or explanation from the specification to support such feature. Such as, none of Fig. 4 and [0057] discusses such feature. Thereby, the executing limitation mentioned above fails to comply with the written description requirement.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 11 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding to Claim 11, the terms “several consecutive operators” and “fewer resources” at lines 1-2 is relative terms which render the claim indefinite. The terms “several” and “fewer” are not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Such as, it is not clear whether the claimed invention would perform the fusing operations on the two consecutive operators having lowest and second lowest resources (or maybe three consecutive operators having lowest, second lowest and third lowest resources) OR the claimed invention would perform the fusing operation on the ten consecutive operators having same amount of lowest resources (or maybe three consecutive operators having same amount of operators having lowest resources) OR there are certain respective threshold values to determine how many consecutive operators should be fused and how many resource amount is consider as fewer or non-fewer.
For the purpose of examination, examiner consider limitation “fusing several consecutive operators in the first data processing models that use fewer resources” as: fusing two or more consecutive operators in the first data processing models.
In addition, the meaning of limitation “executing the integrated operator in a pipelined parallel manner confirming to the parallel execution state” (emphasis added) at last two lines is not clear. According to the context of claim 11, claimed “integrated operator” is defined as merging or fusing several consecutive operators in the first data processing models. According to claim 1 (claim 11 depends on claim 3 and claim 3 depends on claim 1), the claimed “parallel execution state” is defined as “for each operator in each of the second data processing models”. In this way, the claimed executing limitation mentioned above requires executing the integrated operator formed by operators from the first data processing models to confirm the parallel execution state associated with operators from the second data processing models. Such feature does not make sense to one with ordinary skill in the art since it is not confirming to parallel execution state associated with the several consecutive operators from the first data processing models (actually, according to the context of the claims 1, 3, 11, the execution of claimed integrated operator would be performed before obtaining claimed parallel execution state associated with operators from the second data processing models).
For the purpose of examination, examiner interprets the executing limitation mentioned above as: executing the integrated operator in a pipelined parallel manner
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5-8, 9-10 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (CN 107992359 A-English translation provided by Google Patents, hereafter Chen) in views of Ye (CN 111752716 A- English translation provided by Google Patents), Turek et al. (US 5392430 A, hereafter Turek), Liu et al. (US 20210286654 A1, hereafter Liu), Patel et al. (US 20210096915 A1, hereafter Patel) and Catron et al. (US 20240054384 A1, hereafter Catron).
Chen, Ye, Liu, Patel and Catron were cited on the PTO-892 of the previous office action.
Regarding to Claim 1, Chen discloses: A resource allocation method, applied to a server, wherein the method includes:
obtaining tasks executable by the server as first tasks; performing a resource allocation on each first tasks to obtain a quantity of resource used by each task (see [0007] (i.e., from last 9th line of page 2 to line 3 of page 3 of the translation version); “receiving tasks submitted by all users, and adding the tasks into a task queue … 3) respectively calculating resources required by each task in the task queue according to the task type; … 5) scheduling the tasks sequenced in the step 4) one by one, wherein the scheduling process is as follows;”);
obtaining second tasks when the server receives a task request from a user, wherein the second tasks include current tasks of the server and tasks corresponding to the task request from the user (see [0007]-[0008] (i.e., from last 9th line of page 2 to line 5 of page 3 of the translation version); “2) merging the waiting queue into a task queue, and emptying the waiting queue” and “The method for merging the task queues in the step 2) is to merge the task newly submitted by the current user with the waiting task which is finished by scheduling before, and all the merged tasks are taken as the scheduling objects of the current scheduling period”, emphasis added. The language of “the task newly submitted by the current user” indicates there is at least one new task request received from a user, and thus the “the task newly submitted by the current user” can be considered as claimed tasks corresponding to the task request from the user and “the waiting task which is finished by scheduling before” can be considered claimed current tasks of the server);
when the number of the second tasks is greater than one, a coordinated resource allocation sub-method is executed (see [0007]-[0008] (i.e., from last 9th line of page 2 to line 5 of page 3 of the translation version); “merge the task newly submitted by the current user with the waiting task which is finished by scheduling before, and all the merged tasks are taken as the scheduling objects of the current scheduling period”, emphasis added); wherein the coordinated resource allocation sub-method includes:
obtaining a quantity of resource used by each second tasks; allocating resources of the server for each second tasks (see [0007]-[0008] (i.e., from last 9th line of page 2 to line 5 of page 3 of the translation version); “3) respectively calculating resources required by each task in the task queue according to the task type” and “5) scheduling the tasks sequenced in the step 4) one by one, wherein the scheduling process is as follows”. For the new/current scheduling period with merged tasks that including user newly submitted tasks, a new or current scheduling period starts, and thus steps 3-5 discussed at [0007] are performed again for such new/current scheduling period for the merged tasks)
Chen does not disclose: the resource allocation method is applied to a server with a multi-core architecture,
obtaining first data processing models each corresponding to one of the first tasks, wherein each of the first data processing models includes one or more operators;
performing resource allocation on each first task is performing a resource allocation on each operator in each of the first data processing models to obtain a quantity of resource used by each operator by:
sequentially allocating different potential resource quantities in units of kernels of the server ranging from 1 kernel to a preset maximum kernel quantity to each operator;
for each potential resource quantity allocated, executing each operator and obtaining an operator performance corresponding to the potential resource quantity, wherein the operator performance is quantified by a product of an execution time and the potential resource quantity allocated;
selecting the potential resource quantity corresponding to a minimum operator performance as the quantity of resource used by each operator; and
obtaining second data processing models each corresponding to one of the second tasks;
obtaining a quantity of resource used by each second tasks is obtaining a quantity of resource used by each operator in each of the second data processing models based on the quantity of resource used by each operator in each of the first data processing models;
allocating resources of the server for each second tasks is obtaining a scheduling sequence and a parallel execution state for each operator in each of the second data processing models; and allocating resources of the server based on the quantity of resource, scheduling sequence, and parallel execution state for each operator in each of the second data processing model.
However, Ye discloses: A resource allocation method, applied to a server, wherein the method includes: performing resource allocation to one or more tasks (see [0082] (i.e., 12th paragraph of page 6 from the translation version); “the terminal can schedule suitable hardware resources for operators in the deep learning model that match the hardware resources of the terminal”) comprises:
obtaining corresponding data processing models each corresponding to one of the one or more tasks, wherein each of the corresponding data processing models includes one or more operators (see [0109] (i.e., 12th paragraph of page 7 from the translation version); “Usually a deep learning model consists of a set of operators”. Thereby, in order to execute one or more tasks having to one or more deep learning models, it would require to obtain the corresponding deep learning models of the one or more tasks, i.e., claimed data processing models, that each of the corresponding deep learning models in generally includes one or more operators);
performing a resource allocation on each operator in each of the corresponding data processing models to obtain a quantity of resource used by the operator (see [0109]-[0113] (i.e., 12th -16th paragraphs of page 7 from the translation version); “in the process of using the deep learning model, hardware resources are scheduled for the operator according to the target resource scheduling parameters”).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claim invention, to specify the one or more generic tasks from Chen as one or more specified tasks related to deep learning model execution from Ye, since deep learning model type of task execution is well-known application to be used in big data and cloud computing fields.
In addition, Turek discloses: performing a resource allocation on each task in a plurality of tasks to obtain a quantity of resource used by each task by:
sequentially allocating different potential resource quantities in units of resources of the server ranging from 1 resource to a preset maximum resource quantity to each task (see claim 1; “for each said job, creating a plurality, of task schedules for said tasks of said job, each of said task schedules corresponding to a different number of said processors which might possibly be allotted to said job”. Also see lines 37-45 of col. 6, lines 26-29, 34-45 of col. 7; “determines, for each number of processors p between 1 and the total number of processors P, a schedule for each of the tasks within the job q” and “yields the job execution times Tq (p)=t1 (p) for each number of processors p between 1 and P”);
for each potential resource quantity allocated, executing each task and obtaining an operator performance corresponding to the potential resource quantity, wherein the task performance is quantified by a product of an execution time and the potential resource quantity allocated (see claims 1 and 5; “(c) determining an estimated job execution time for each of said task schedules; (d) using said estimated job execution times for each of said jobs and for each different number of processors which might be allocated to each of said jobs” and “wherein step (d) includes the step of computing the product of estimated job execution time and number of processors corresponding thereto for each of said task schedules” . Also see lines 38-49 of col. 4; “the one with the smallest product of estimated job execution time and number of processors”);
selecting the potential resource quantity corresponding to a minimum task performance as the quantity of resource used by each task (see claims 1 and 5; “determining an allotment of processors for each of said jobs”, “an initial allotment of processors for each of said jobs corresponds to a minimum one of such computed products for each of said jobs”. Also see lines 38-49 of col. 4; “the one with the smallest product of estimated job execution time and number of processors used is preferred) and the number of processors corresponding to this member is tentatively selected as an initial number of processors allotted to that job”).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claim invention, to modify resource allocation performed on tasks from the combination of Chen and Ye by including allocating optimized number of resources on the tasks from Turek, since it would provide a mechanism of allocating optimized and smallest amount of resources to each task (see lines 38-49 of col. 4 from Turek).
In addition, Liu discloses: allocating resource quantities in units of kernels of the server (see [0040]; “The graphics processing unit kernel, as a dedicated processing resource, is the most basic processing unit, which is also known as streaming processor (SP). Instructions and jobs are ultimately processed in the graphics processing unit kernel”. Also see [0032]; “in the context of the present disclosure, various example implementations of the present disclosure will be described with a deep learning-based computing job as a specific example”).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claim invention, to modify the resource allocation on the operators of the deep learning model from the combination of Chen, Ye and Turek by including allocating the most basic processing unit kernel for executing deep learning jobs from Liu, since a kernel is known as computations in a neural network (see [0026] from Liu; “The vertices (or nodes) of the computation graph define computations (often called kernels) in a neural network”).
In this way, the combination of Chen, Ye, Turek and Liu discloses: A resource allocation method, applied to a server (see [0007] from Chen (i.e., from last 9th line of page 2 to line 3 of page 3 of the translation version) and [0082] from Ye (i.e., 12th paragraph of page 6 from the translation version); “the terminal can schedule suitable hardware resources for operators in the deep learning model that match the hardware resources of the terminal”), wherein the method includes:
obtaining tasks executable by the server as first tasks; obtaining first data processing models each corresponding to one of the first tasks, wherein each of the first data processing models includes one or more operators (see [0007] from Chen (i.e., from last 9th line of page 2 to line 3 of page 3 of the translation version) and [0109] from Ye (i.e., 12th paragraph of page 7 from the translation version); “receiving tasks submitted by all users, and adding the tasks into a task queue” and “Usually a deep learning model consists of a set of operators”. At the combination system, the executable tasks are the tasks related to executing corresponding deep learning model that each corresponding deep learning model having a set of operators);
performing a resource allocation on each operator in each of the first data processing models to obtain a quantity of resource used by each operator by (see [0109]-[0113] from Ye (i.e., 12th -16th paragraphs of page 7 from the translation version); “target resource scheduling parameters set for each operator in the deep learning model … in the process of using the deep learning model, hardware resources are scheduled for the operator according to the target resource scheduling parameters”) :
sequentially allocating different potential resource quantities in units of kernels of the server ranging from 1 kernel to a preset maximum kernel quantity to each operator (see claim 1 from Turek; “for each said job, creating a plurality, of task schedules for said tasks of said job, each of said task schedules corresponding to a different number of said processors which might possibly be allotted to said job”. Also see lines 37-45 of col. 6, lines 26-29, 34-45 of col. 7 from Turek; “determines, for each number of processors p between 1 and the total number of processors P, a schedule for each of the tasks within the job q” and “yields the job execution times Tq (p)=t1 (p) for each number of processors p between 1 and P”. Also see [0040] from Liu for the resource quantity is allocated via kernels as basic units of resources);
for each potential resource quantity allocated, executing each operator and obtaining an operator performance corresponding to the potential resource quantity, wherein the operator performance is quantified by a product of an execution time and the potential resource quantity allocated (see claims 1 and 5 from Turek; “(c) determining an estimated job execution time for each of said task schedules; (d) using said estimated job execution times for each of said jobs and for each different number of processors which might be allocated to each of said jobs” and “wherein step (d) includes the step of computing the product of estimated job execution time and number of processors corresponding thereto for each of said task schedules” . Also see lines 38-49 of col. 4 from Turek; “the one with the smallest product of estimated job execution time and number of processors”);
selecting the potential resource quantity corresponding to a minimum operator performance as the quantity of resource used by each operator (see claims 1 and 5 from Turek; “determining an allotment of processors for each of said jobs”, “an initial allotment of processors for each of said jobs corresponds to a minimum one of such computed products for each of said jobs”. Also see lines 38-49 of col. 4 from Turek; “the one with the smallest product of estimated job execution time and number of processors used is preferred) and the number of processors corresponding to this member is tentatively selected as an initial number of processors allotted to that job”).
obtaining second tasks when the server receives a task request from a user, wherein the second tasks include current tasks of the server and tasks corresponding to the task request from the user (see [0007]-[0008] from Chen (i.e., from last 9th line of page 2 to line 5 of page 3 of the translation version); “2) merging the waiting queue into a task queue, and emptying the waiting queue” and “The method for merging the task queues in the step 2) is to merge the task newly submitted by the current user with the waiting task which is finished by scheduling before, and all the merged tasks are taken as the scheduling objects of the current scheduling period”. At the combination system, once finishing task scheduling operations on the current existing tasks and receiving new tasks from user, the combination system would obtain new group of tasks for new tasks scheduling, wherein such new group of tasks include current tasks from the finished task scheduling operations, i.e., claimed current tasks of the server, and the new tasks submitted from users, i.e., tasks corresponding to the task request from the user);
when the number of the second tasks is greater than one, a coordinated resource allocation sub-method is executed (see [0007]-[0008] from Chen (i.e., from last 9th line of page 2 to line 5 of page 3 of the translation version); “merge the task newly submitted by the current user with the waiting task which is finished by scheduling before, and all the merged tasks are taken as the scheduling objects of the current scheduling period”); wherein the coordinated resource allocation sub-method includes:
obtaining second data processing models each corresponding to one of the second tasks (see [0007] from Chen (i.e., from last 9th line of page 2 to line 3 of page 3 of the translation version) and [0109] from Ye (i.e., 12th paragraph of page 7 from the translation version); “receiving tasks submitted by all users, and adding the tasks into a task queue” and “Usually a deep learning model consists of a set of operators”. At the combination system, the executable or requested tasks are the tasks related to executing corresponding deep learning model that each corresponding deep learning model having a set of operators, and thus it would require to obtaining corresponding deep learning models of the merged tasks at the current/new scheduling period);
obtaining a quantity of resource used by each operator in each of the second data processing models (see [0109]-[0113] from Ye (i.e., 12th -16th paragraphs of page 7 from the translation version); “target resource scheduling parameters set for each operator in the deep learning model”. At the current/new scheduling period, the combination system is also required to obtain the target resource scheduling parameter, i.e., claimed quantity of resource, for each operator of the corresponding deep learning model of the merged tasks)
obtaining a scheduling sequence [and a parallel execution state] for each operator in each of the second data processing models; and allocating resources of the server based on the quantity of resource, scheduling sequence [, and parallel execution state] for each operator in each of the second data processing model (see [0109]-[0113] from Ye (i.e., 12th -16th paragraphs of page 7 from the translation version); “target resource scheduling parameters set for each operator in the deep learning model … in the process of using the deep learning model, hardware resources are scheduled for the operator according to the target resource scheduling parameters”. Note: it is understood that some of the operators in the deep learning model have a particular scheduling/execution sequence, such as the operator to generate output of the deep learning model has to be scheduled/executed after the operator to obtain input of the deep learning model).
The combination of Chen, Ye, Turek and Liu does not disclose:
obtaining a quantity of resource used by each operator in each of the second data processing models based on the quantity of resource used by each operator in each of the first data processing models;
obtaining a parallel execution state for each operator in each of the second data processing models; and allocating resources of the server based on parallel execution state for each operator in each of the second data processing model.
However, Patel discloses: obtaining a quantity of resource used by each operation of current period based on the quantity of resource used by each operation of previous period (see [0029] and [0073]; “a resource predictor 102 that predicts the maximum required resources for recurring jobs … associated telemetry from previous job executions. Using this data, the system 100 learns the models for the resource predictor 102 for each recurring job at Step 1” and “predicting the peak resource requirement at 906 may further include predicting the peak resource requirement using a machine learning model that is trained using past feature values and past actual peak resource usage information of past jobs that are associated with the hash”).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claim invention, to modify the processes of retrieving resource number allocated to each operator at the combination of Chen, Ye, Turek and Liu by including the processes of predicting resource requirement for each job operations from historical information from Patel, since it would provide a method of continuously learns from the past workloads and may therefore optimize performance for different subsets of the workload and fix errors in the early predictions (see [0030] from Patel).
In addition, Catron discloses: a resource allocation method, applied to a server with a multi-core architecture (see [0039] and [0043]; “partitioning of the machine learning model network across the accelerators of server 102” and “allocating computing cores of a machine learning accelerator hardware unit between different operators of the machine learning model network”), wherein the method includes:
obtaining a scheduling sequence and a parallel execution state for each operator in each of the second data processing models; and allocating resources of the server based on scheduling sequence, and parallel execution state for each operator in each of the second data processing model (see [0039]-[0043]; “a machine learning model network is analyzed to identify types of operations and dependencies. The operations and dependencies are associated with different portions of the machine learning model network” and “allowing parallelization and pipelining includes allocating computing cores of a machine learning accelerator hardware unit between different operators of the machine learning model network … assigning a first specified number of cores to sparse lookups and a second specified number of cores to MLP computation, sparse lookups can run in parallel across different machine learning accelerator hardware units and MLP computation can execute simultaneously with sparse lookups in a pipelined fashion”).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claim invention, to modify the operator executions in deep learning models from the combination of Chen, Ye, Turek, Liu and Patel by including processes of analyzing a machine learning model to allow parallelization and pipelining executions on the machine learning model from Catron, and thus the combination of Chen, Ye, Turek, Liu, Patel and Catron would disclose the missing limitations from the combination of Chen, Ye, Turek and Liu, since it would provide a high efficiency resource usage for a machine learning model (see [0028] from Catron; “the MLP portion must find enough parallelism to saturate all the cores on the accelerator in order to achieve high efficiency, which may not always be possible. Such parallelism is not always easy to find and exploit. This problem is also addressed by concurrent execution and pipelining”).
Regarding to Claim 5, the rejection of Claim 1 is incorporated and further the combination of Chen, Ye, Turek, Liu, Patel and Catron discloses: wherein after obtaining the parallel execution state for each operator in each of the second data processing models (see Fig. 4, [0045]-[0046] from Catron; “an initial partitioning of a machine learning model network across a plurality of different machine learning accelerator hardware units is performed” and “performance associated with the initial partitioning is tracked”), the coordinated resource allocation sub-method further includes:
obtaining an interference model between operators in each of the second data processing models (see [0046] from Catron; “performance associated with the initial partitioning is tracked”, “compute times and data transfer times of the different machine learning operators of the machine learning model network are tracked by the plurality of different machine learning accelerator hardware units … the costs are tracked during one or more inference executions of the machine learning model network”. Note: current claimed “interference model between operators” are not further specified/claimed, and thus the performance tracking for the compute times and data transfer times of the different machine learning operators discussed at [0046] from Catron are reasonable to be considered as claimed interference model between operators);
adjusting, based on the interference model, the scheduling sequence and the parallel execution state for each of the operators in each of the second data processing models (see [0047] from Catron; “a new partitioning of the machine learning model network is determined based on the tracked performance … the new partitioning may separate operators with long compute times into different partitions”).
Regarding to Claim 6, the rejection of Claim 1 is incorporated and further the combination of Chen, Ye, Turek, Liu, Patel and Catron discloses: wherein after obtaining the scheduling sequence and the parallel execution state for each of the operators in each of the second data processing models (see Fig. 4, [0045]-[0046] from Catron; “an initial partitioning of a machine learning model network across a plurality of different machine learning accelerator hardware units is performed” and “performance associated with the initial partitioning is tracked”), the coordinated resource allocation sub-method further includes:
obtaining a resource utilization status of the server based on the quantity of resource, scheduling sequence, and parallel execution state for each of the operators in each of the second data processing models (see [0046] from Catron; “performance associated with the initial partitioning is tracked”, “compute times and data transfer times of the different machine learning operators of the machine learning model network are tracked by the plurality of different machine learning accelerator hardware units … the costs are tracked during one or more inference executions of the machine learning model network”);
adjusting the quantity of resource used by at least one operator in each of the second data processing models based on the resource utilization status of the server (see [0047] from Catron; “a new partitioning of the machine learning model network is determined based on the tracked performance … the new partitioning may separate operators with long compute times into different partitions”. Also see [0043] from Catron; “allowing parallelization and pipelining includes allocating computing cores of a machine learning accelerator hardware unit between different operators of the machine learning model network … assigning a first specified number of cores to sparse lookups and a second specified number of cores to MLP computation, sparse lookups can run in parallel across different machine learning accelerator hardware units and MLP computation can execute simultaneously with sparse lookups in a pipelined fashion”. If the parallelization and pipelining among the operators are changed, then the quantity of resources to be used by certain operators are also changed. Such as, before changing the parallelization and pipelining, two operators may be executed concurrently as a whole to use a first amount of resource; however, these two operators may be executed sequenced that each of these two operators would use a second amount of resources that is less than the first amount).
Regarding to Claim 7, the rejection of Claim 1 is incorporated and further the combination of Chen, Ye, Turek, Liu, Patel and Catron disclose: the obtaining of the second tasks includes:
stopping a currently executed resource allocation scheme (see [0007]-[0008] from Chen (i.e., from last 9th line of page 2 to line 5 of page 3 of the translation version); “returning to the step 1) and continuing the next scheduling period”. The language of “continuing the next scheduling period” indicating the currently executed resource allocation/scheduling scheme is completed/finished, and then the system is going to the next/new resource allocation/scheduling scheme);
obtaining unfinished tasks and unfinished sub-tasks from the current tasks of the server; and configuring the tasks corresponding to the task request from the user, the unfinished tasks, and the unfinished sub-tasks as the second tasks (see [0007]-[0008] from Chen (i.e., from last 9th line of page 2 to line 5 of page 3 of the translation version); “2) merging the waiting queue into a task queue, and emptying the waiting queue” and “merging the task queues in the step 2) is to merge the task newly submitted by the current user with the waiting task which is finished by scheduling before, and all the merged tasks are taken as the scheduling objects of the current scheduling period”).
Regarding to Claim 8, the rejection of Claim 1 is incorporated and further the combination of Chen, Ye, Turek, Liu, Patel and Catron discloses: wherein the resource allocation method is executed in units of kernels of the server (see [0040] from Liu; “The graphics processing unit kernel, as a dedicated processing resource, is the most basic processing unit, which is also known as streaming processor (SP). Instructions and jobs are ultimately processed in the graphics processing unit kernel”. At the combination system, the jobs or operators are allocated with kernels as units of resources of a system/server for execution, and thus the claimed resource allocation method, i.e., at least the steps/actions of allocating the resources for each operator in the first data processing models and the second data processing models from claim 1 are executed in units of kernels of the server).
Regarding to Claim 9, Claim 9 is a product claim corresponds to method Claim 1 and is rejected for the same reason set forth in the rejection of Claim 1 above (note: also see [0098] and claim 17 from Patel for claimed “A non-transitory computer-readable storage medium, configured to store a computer program”).
Regarding to Claim 10, Claim 10 is a system claim corresponds to method Claim 1 and is rejected for the same reason set forth in the rejection of Claim 1 above (note: for claimed “a display”, see [0054] and [0057] from Catron; “processor 602 controls the reception and manipulation of input data, and the output and display of data on output devices (e.g., display 618)”; also see [0092] and [0096] from Patel; “The computing device 10 may also include a user interface component 12 operable to receive inputs from a user of the computing device 10 and further operable to generate outputs for presentation to the user (e.g., via a display interface to a display device)”).
Regarding to Claim 14, the rejection of Claim 6 is incorporated and further the combination of Chen, Ye, Turek, Liu, Patel and Catron discloses: wherein adjusting the quantity of resource used by the at least one operator in each of the second data processing models based on the resource utilization status of the server comprises: real-time monitoring the resource utilization status of the server to calculate a quantity of idle kernels; and allocating the idle kernels to operators currently being executed (see [0037] and [0043] from Catron; “prevents idle compute resources when a portion of a machine learning model network (e.g., sparse lookups) is not compute intensive enough to keep all cores of an accelerator occupied” and “assigning a first specified number of cores to sparse lookups and a second specified number of cores to MLP computation, sparse lookups can run in parallel across different machine learning accelerator hardware units and MLP computation can execute simultaneously with sparse lookups in a pipelined fashion”. Also see [0038] from Liu; “allocate dedicated processing resource 160 to client 120 based on the quantity of dedicated processing resources requested by client 120 and available dedicated processing resources in system 100”).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (CN 107992359 A-English translation provided by Google Patents, hereafter Chen) in views of Ye (CN 111752716 A- English translation provided by Google Patents), Turek et al. (US 5392430 A, hereafter Turek), Liu et al. (US 20210286654 A1, hereafter Liu), Patel et al. (US 20210096915 A1, hereafter Patel) and Catron et al. (US 20240054384 A1, hereafter Catron) and further in view of Zhang et al. (US 20220121903 A1, hereafter Zhang).
Chen, Ye, Liu, Patel, Catron and Zhang were cited on the PTO-892 of the previous office action.
Regarding to Claim 3, the rejection of Claim 1 is incorporated, the combination of Chen, Ye, Turek, Liu, Patel and Catron does not disclose: performing operator fusion or operator slicing on each operator in each of the first data processing models based on the quantity of resource used by each operator.
However, Zhang discloses: performing operator fusion or operator slicing on each operator in each of the first data processing models based on the quantity of resource used by each operator (see [0164]; “the nucleus number of the multi-core structure is usually an integer power of 2, for example, 1, 2, 4, 8, and 16. A task whose degree of parallelism is not an integer power of 2 will often cause “fragments” in the core scheduling. Therefore, the number of the split sub-operators should be the integer power of 2”).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claim invention, to modify the operation executions of the deep learning model from the combination of Chen, Ye, Turek, Liu, Patel and Catron by including splitting an operator into a number according to integer power of 2 from Zhang, and thus the combination of Chen, Ye, Turek, Liu, Patel, Catron and Zhang would disclose the missing limitations from the combination of Chen, Ye, Turek, Liu, Patel and Catron, since it would provide an operator splitting mechanism of avoiding fragments in core scheduling (see [0164] from Zhang).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (CN 107992359 A-English translation provided by Google Patents, hereafter Chen) in views of Ye (CN 111752716 A- English translation provided by Google Patents), Turek et al. (US 5392430 A, hereafter Turek), Liu et al. (US 20210286654 A1, hereafter Liu), Patel et al. (US 20210096915 A1, hereafter Patel) and Catron et al. (US 20240054384 A1, hereafter Catron) and further in view of Sanjabi et al. (US 20180143858 A1, hereafter Sanjabi).
Chen, Ye, Liu, Patel, Catron and Sanjabi were cited on the PTO-892 of the previous office action.
Regarding to Claim 4, the rejection of Claim 1 is incorporated, the combination of Chen, Ye, Turek, Liu, Patel and Catron does not disclose: the obtaining of the scheduling sequence for each operator in each of the second data processing models includes:
obtaining a performance model for each operator in each of the second data processing models, wherein the performance model includes an execution time of the operator;
obtaining a service quality requirement for each of the second tasks; and
obtaining the scheduling sequence for each operator in each of the second data processing models based on the service quality requirement for each of the second tasks and the performance model.
However, Sanjabi discloses: the obtaining of the scheduling sequence for each subtasks includes:
obtaining a performance model for each subtask, wherein the performance model includes an execution time of the subtask; obtaining a service quality requirement for each of the second tasks; obtaining the scheduling sequence for each subtask based on the service quality requirement for each of the second tasks and the performance model (see [0075]-[0076]; “determines the distribution over time of the resources required by each subtask by selecting an order in which to assign resource allocations to each subtask, a resource allocation over time for each subtask, and/or a start time for each subtask”) and “the jobs that are on the critical path of workflows with early deadlines are ordered, shaped, and placed, before less-critical jobs (e.g. jobs that are part of workflows with less-pressing deadlines)”).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claim invention, to modify the scheduling sequence of the operators of one or more tasks from the combination of Chen, Ye, Turek, Liu, Patel and Catron by including processes of scheduling tasks and subtasks based on corresponding deadline from Sanjabi, and thus the combination of Chen, Ye, Turek, Liu, Patel, Catron and Sanjabi would disclose the missing limitations from the combination of Chen, Ye, Turek, Liu, Patel and Catron, since it would provide a mechanism of ensuring jobs having early deadlines can be scheduled before jobs having less-pressing deadlines (see [0076] from Sanjabi).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (CN 107992359 A-English translation provided by Google Patents, hereafter Chen) in views of Ye (CN 111752716 A- English translation provided by Google Patents), Turek et al. (US 5392430 A, hereafter Turek), Liu et al. (US 20210286654 A1, hereafter Liu), Patel et al. (US 20210096915 A1, hereafter Patel) and Catron et al. (US 20240054384 A1, hereafter Catron) and further in view of Horowitz et al. (US 20180300381 A1, hereafter Horowitz).
Chen, Ye, Liu, Patel and Catron were cited on the PTO-892 of the previous office action.
Regarding to Claim 11, the rejection of Claim 3 is incorporated and the combination of Chen, Ye, Turek, Liu, Patel, Catron and Zhang disclose: the operator fusion comprises:
fusing several [consecutive] operators in the first data processing models that use fewer resources, belong to a same first task, and are within a maximum available resource limit of the server; and allocating a total resource quantity to the integrated operator based on a sum of resources used by the several [consecutive] operators, and executing the several operator in a pipelined parallel manner confirming to the parallel execution state (see [0031], [0043] from Catron; “allocating computing cores of a machine learning accelerator hardware unit between different operators of the machine learning model network … assigning a first specified number of cores to sparse lookups and a second specified number of cores to MLP computation, sparse lookups can run in parallel across different machine learning accelerator hardware units and MLP computation can execute simultaneously with sparse lookups in a pipelined fashion”. Also see claim 16; “wherein allowing pipelining of the execution of the machine learning model network includes concurrently executing a memory bandwidth intensive portion of the machine learning model network and a compute intensive portion of the machine learning model network on at least one machine learning accelerator hardware unit of the plurality of different machine learning accelerator hardware units”).
The combination of Chen, Ye, Turek, Liu, Patel, Catron and Zhang does not disclose: the fusing operation is fusing several consecutive operators into a single integrated operator.
However, Horowitz disclose: fusing several consecutive operators into a singled integrated operator (see [0017]; “The system may optimize functions …coalesce pipeline stages together (e.g., combining sequential operators into a single operator),).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claim invention, to modify the pipelined execution different portions/operators of the machine learning model from the combination of Chen, Ye, Turek, Liu, Patel, Catron and Zhang by including combining sequential operators into a single operator from Horowitz, and thus the combination of Chen, Ye, Turek, Liu, Patel, Catron, Zhang and Horowitz would disclose the missing limitations from the combination of Chen, Ye, Turek, Liu, Patel, Catron and Zhang, since it would provide a mechanism of managing multiple operations easier by considering such multiple operations as one single operation.
Note: claim 11 depends on claim 3 and claim 3 is a method claim. Thereby, when claim 3 is rejected under the BRI of performing operator slicing instead of performing operator fusion, claim 11 that discussed operator fusion under BRI is already rejected in view of claim 3.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (CN 107992359 A-English translation provided by Google Patents, hereafter Chen) in views of Ye (CN 111752716 A- English translation provided by Google Patents), Turek et al. (US 5392430 A, hereafter Turek), Liu et al. (US 20210286654 A1, hereafter Liu), Patel et al. (US 20210096915 A1, hereafter Patel) and Catron et al. (US 20240054384 A1, hereafter Catron) and further in view of Hernandez et al. (US 11783256 B1, hereafter Hernandez).
Chen, Ye, Liu, Patel and Catron were cited on the PTO-892 of the previous office action.
Regarding to Claim 12, the rejection of Claim 3 is incorporated and the combination of Chen, Ye, Turek, Liu, Patel, Catron and Zhang discloses: the operator slicing comprises: identifying an operator in the first data processing models whose running time [exceeds a preset threshold] as a long-running operator (see [0047]-[0048] from Catron; “when tracked costs are based at least in part on compute time, the new partitioning may separate operators with long compute times into different partitions”);
slicing the long-running operator into two or more sub-operators within a maximum available resource limit of the server and without affecting an overall performance of the first data processing models; and allocating resource quantities to each of the sub-operators based on a current kernel availability of the server (see [0037] and [0047] from Catron; “This allows for exploitation of coarse grain parallelism and prevents idle compute resources when a portion of a machine learning model network (e.g., sparse lookups) is not compute intensive enough to keep all cores of an accelerator occupied” and “the new partitioning may separate operators with long compute times into different partitions … This process can be continued iteratively until specified conditions are met to indicate further re-partitioning would not significantly improve performance”. Since the combination system would like to prevent idle compute resources and keep all cores of an accelerator occupied, and thus the new partitioning would slice or separate the long-running operator within a maximum available resource limit of the server).
The combination of Chen, Ye, Turek, Liu, Patel, Catron and Zhang does not disclose:
the long-running operator is identified as an operator whose running time exceeds a preset threshold.
However, Hernandez discloses: the task slicing comprises: identifying a task whose running time exceeds a preset threshold as a long-running task; slicing the long-running task into two or more sub-tasks (see lines 34-46 of col. 1; “identifying at least one computational task within the list of computational tasks having a corresponding load time that is above a load time threshold. The method further comprises replacing the at least one computational task within the list of computational tasks with a plurality of sub-tasks configured to collectively achieve the at least one computational task”).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claim invention, to modify the identification and partitioning of long-running operator of the machine learning model from the combination of Chen, Ye, Turek, Liu, Patel, Catron and Zhang by including identifying a long-running task based on a threshold value and replacing the long-running job with multipole sub-tasks from Hernandez, and thus the combination of Chen, Ye, Turek, Liu, Patel, Catron, Zhang and Hernandez would disclose the missing limitations from the combination of Chen, Ye, Turek, Liu, Patel, Catron and Zhang, since it would provide a standard to identify a long-running task via a threshold value (see lines 34-46 of col. 1 from Hernandez).
Allowable Subject Matter
Claim 13 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 13 contains allowability subject matter of “wherein obtaining the interference model and adjusting the scheduling sequence and the parallel execution state comprises: quantifying shared resource requirements between operators in the second processing models; performing performance testing on the operators using randomly generated operator parameters or common network operator parameters; recording an interference status between parallel-executed operators; building the interference model using linear regression models or neural network modules; and during resource allocation, if the interference model indicates high interference between two operators, switching their execution parallel to serial”.
Some of related new references found:
Moir et al. (US 20040015510 A1) discloses: concurrently executing push-type and pop-type access operations; detecting interference with a particular execution of one of the access operations using a single-target synchronization primitive (see claim 43).
Moir et al. (US 7328316 B2) discloses wherein at least some concurrently executed access operations interfere with each other; and wherein the interfering concurrently executed access operations are retried (see claim 35). Moir et al also discloses: transaction A can determine in advance that it will interfere with transaction B, it can decide, based on the policy implemented by its contention manager (discussed in the next section), whether to abort B or to give B a chance to finish (see lines 1-6 of col. 13).
Wang (CN 106712981 A-English translation provided by Google Patents) discloses: it is necessary to which the multiple application systems of control are to same The concurrently access of one shared resource, resource data is destroyed to prevent interfering with each other between different application systems Uniformity (see [0002]).
Zhang et al. (CN 104216764 A-English translation provided by Google Patents) discloses: Multiple threads in the same process share the same resources. Even if the initial conditions of the program are the same, due to the interference of internal and external environmental factors such as embedded system interrupts, operation delays, and noise, the execution of parallel programs in the system is greatly affected and changed (see [0002]).
Ramalingam et al. (US 20100169618 A1) discloses: ensuring non-interference between concurrent clients using some shared resource by leveraging a sequential proof for sequential code to derive concurrent control. A synthesizer component can analyze a sequential proof related to a portion of sequential code in order to automatically and systematically generate concurrency control for particular execution points in order to adapt the sequential code to a concurrent client, setting, or environment (see [0004]).
Nagano et al. (JPH0287232A-English translation provided by Google Patents) discloses: a partial interference detection phase in which, after executing rule matching in each processor, interference detection is performed on the matching results of the processor (see claim 1).
None of the related new references found alone or in combination (or in combination with previous cited prior art references) would actually teach the limitations from claim 13 identified above.
Response to Arguments
Applicant’s arguments, filed 12/24/2025, with respect to rejections of claims 1, 3-10 under 35 U.S.C. 103 have been full considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Compact Prosecution
Examiner tried to contact Power of Attorney Xiaofei Xue (Reg. # 65470) at the phone # of 503-616-4800 indicated at the Remarks submitted by 12/24/2025 during 1/21/2026-1/22/2026 to discuss Examiner’s amendment. However, Examiner received the message of “the number you have dialed is not in service please check the number and try your call again”. In addition, Examiner also tried to contact Attorney Xiaofei Xue at 408-656-4162 that recorded at USPTO database. However, Examiner did not receive any message back.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chaudhuri et al. (US 20160125118 A1) discloses: groupings or blocks of sequential operations can be identified for parallel execution on two or more processing elements (see [0021]).
Liang (US 20010044818 A1) discloses: it should be noted that although the steps in FIG. 3 are demonstrated as sequential, the text and image analysis engines described below may instead be designed to operate in parallel. In particular, parallel operation may be desirable when large processing resources are available, while the serial approach described below may be preferable when there is a desire to conserve processing resources (see [0028]).
Hackborn et al. (US 20150095521 A1) disclose: determining a memory usage rating for the process based on the memory usage value and a run time for the process, wherein the run time indicates how long the process runs during the time period, and wherein the memory usage rating for the process represents a multiplicative product of (i) an amount of memory and (ii) an amount of time (see claim 1)
Benhase et al. (US 20030061264 A1) discloses: CPU resources are allocated in a manner that dedicates a minimum number of CPU resources to handle I/O tasks at an acceptable level of performance and, at the same time, allocates a minimum number of CPU resources as shared to make resources always available to handle the application tasks 124 generated by the application programs 116 a, b . . . n (see [0031]).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHI CHEN whose telephone number is (571)272-0805. The examiner can normally be reached on M-F from 9:30AM to 5:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, April Y Blair can be reached on 571-270-1014. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Zhi Chen/
Patent Examiner, AU2196
/HIREN P PATEL/Primary Examiner, Art Unit 2196