DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
2. Claim(s) 1-6, 12, 16-17, and 19 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by HUANG et al. (US Patent/PGPub. No. 20240355258).
Claim 1 (Original),
HUANG et al. teach
an array substrate ([0079], FIG. 1, i.e. the substrate), comprising a pixel array ([0051], FIG. 1, i.e. pixel units arranged in an array) formed by a plurality of rows ([0053], FIG. 2, i.e. each sub-pixel row) and a plurality of columns of sub-pixels ([0053], FIG. 2, i.e. adjacent columns of some of pixels), wherein a plurality of gate lines ([0051], FIG. 1, i.e. plurality of gate lines (for example, GA1, GA2, GA3, . . . GA13, GA14)) and a plurality of data lines ([0051], FIG. 1, i.e. plurality of data lines (for example, DA1, DA2, DA3, DA4, DA5)) intersect to define (FIG. 2, i.e. as shown by the figure(s)) the plurality of rows and the plurality of columns of sub-pixels (i.e. please see above citation(s)),
each row of sub-pixels ([0053], FIG. 2, i.e. first sub-pixel row) among the plurality of rows of sub-pixels (i.e. please see above citation(s)) is connected with two adjacent gate lines ([0053], FIG. 2, i.e. corresponds to gate lines GA1 and GA2) among the plurality of gate lines (i.e. please see above citation(s));
at least one data line ([0054], FIG. 2, i.e. R11 and G11 are connected to DA1) among the plurality of data lines (i.e. please see above citation(s)) is connected with two adjacent columns of sub-pixels ([0054], FIG. 2, i.e. R11 and G11 are connected to DA1) among the plurality of columns of sub-pixels (i.e. please see above citation(s));
the plurality of gate lines are configured to turn on ([0051], FIG. 1, i.e. driving the gate lines GA1, GA2, GA3, . . . GA13, GA14, to control the connected transistors to be turned on) the plurality of rows of sub- pixels, and the plurality of data lines are configured to charge the plurality of columns of sub-pixels that are turned on ([0051], FIG. 1, i.e. data lines is input to the sub-pixels through the turned-on transistors to charge the sub-pixels);
the plurality of rows of sub-pixels (i.e. please see above citation(s)) comprise a plurality of groups of sub-pixels ([0054], FIG. 2, i.e. divided into a plurality of sub-pixel groups), each group of sub-pixels comprises part ([0054], FIG. 2, i.e. red sub-pixel R11 … blue sub-pixel B11) of the plurality of rows of sub-pixels (i.e. please see above citation(s)), each row of sub-pixels ([0054], FIG. 2, i.e. first sub-pixel row) among the part of the plurality of rows of sub-pixels (i.e. please see above citation(s)) comprises sub-pixels connected with a same gate line ([0054], FIG. 2, i.e. red sub-pixel R11 is electrically connected to the gate line GA1 … blue sub-pixel B11 is electrically connected to the gate line GA1), and charging times ([0062], FIG. 4, i.e. B11 is charged) of the part of the plurality of rows of sub-pixels are overlapped ([0062], FIG. 4, i.e. “data voltage Vb11” overlapped in ga1 and ga2 during T11 as shown by the figure(s));
the part of the plurality of rows of sub-pixels (i.e. please see above citation(s)) comprises a first part ([0062], FIG. 2 &4, i.e. “data voltage Vb11” of ga1 as shown by the figure(s)) of the plurality of rows of sub-pixels (i.e. please see above citation(s)) and a second part ([0062]-[0063], FIG. 2 &4, i.e. “data voltage Vb11” and “data voltage Vr12” of ga2 as shown by the figure(s)) of the plurality of rows of sub-pixels (i.e. please see above citation(s)), a charging time ([0062]-[0063], FIG. 2 &4, i.e. ga2 during T11&T12 as shown by the figure(s)) of the second part of the plurality of rows of sub-pixels (i.e. please see above citation(s)) is longer than ([0062]-[0063], FIG. 2 &4, i.e. T11&T12 > T11 as shown by the figure(s)) a charging time ([0062]-[0063], FIG. 2 &4, i.e. ga1 during T11 as shown by the figure(s)) of the first part of the plurality of rows of sub-pixels (i.e. please see above citation(s)),
during a first time period ([0062]-[0063], FIG. 2 &4, i.e. during T11 as shown by the figure(s)) in which the charging times overlap ([0062]-[0063], FIG. 2 &4, i.e. overlap during T11 for ga1 and ga2 as shown by the figure(s)), a same data signal ([0062], FIG. 2 &4, i.e. “data voltage Vb11”) is written into the first part ([0062]-[0063], FIG. 2 &4, i.e. during T11 of ga1 as shown by the figure(s)) of the plurality of rows of sub-pixels (i.e. please see above citation(s)) and the second part ([0062]-[0063], FIG. 2 &4, i.e. during T11 of ga2 as shown by the figure(s)) of the plurality of rows of sub-pixels (i.e. please see above citation(s)),
during a second time period ([0062]-[0063], FIG. 2 &4, i.e. during T12 as shown by the figure(s)) in which the charging times do not overlap ([0062]-[0063], FIG. 2 &4, i.e. T12 of ga1 and ga2 do not overlap as shown by the figure(s)), a data signal ([0062]-[0063], FIG. 2 &4, i.e. “data voltage Vb11” and “data voltage Vr12” of ga2 as shown by the figure(s))) written into the second part of the plurality of rows of sub-pixels (i.e. please see above citation(s)) is at least partially the same ([0062], FIG. 2 &4, i.e. “data voltage Vb11” being the same data written during T11 for both ga1 and ga2 as shown by the figure(s)) as the data signal written during the first time period (i.e. please see above citation(s)).
Claim 2 (Original),
HUANG et al. teach
the array substrate according to claim 1, wherein in the part of the plurality of rows of sub-pixels (i.e. please see above citation(s)), a same data line ([0053], FIG. 2, i.e. data line DA1) is connected with a plurality of sub-pixels corresponding to a same color (FIG. 2, i.e. R11, R31, R51, and R71 as shown by the figure(s)).
Claim 3 (Currently Amended),
HUANG et al. teach
the array substrate according to claim 1, wherein the charging time of the first part of the plurality of rows of sub-pixels (i.e. please see above citation(s)) is a charging time ([0062], FIG. 2, i.e. time period T11) of one row ([0062], FIG. 2, i.e. gate line GA1) of sub-pixels, the charging time of the second part of the plurality of rows of sub-pixels (i.e. please see above citation(s)) is a charging time ([0062], FIG. 2, i.e. time period T11 corresponding to the high level of the signal ga1 … the time period T11, the signal ga2 on the second gate line GA2 outputs a high-level gate-on signal) of two rows of sub-pixels ([0062], FIG. 2, i.e. time period T11 corresponding to the high level of the signal ga1 … the time period T11, the signal ga2 on the second gate line GA2 outputs a high-level gate-on signal), and the first part ([0062], FIG. 2 &4, i.e. “data voltage Vb11” of ga1 as shown by the figure(s)) of the plurality of rows of sub-pixels (i.e. please see above citation(s)) and the second part ([0062], FIG. 2 &4, i.e. “data voltage Vb11” of ga2 as shown by the figure(s)) of the plurality of rows of sub-pixels (i.e. please see above citation(s)) start being charged simultaneously ([0062], FIG. 2 &4, i.e. data voltage Vb11 is simultaneously input into the red sub-pixel R12 to pre-charge the red sub-pixel R12, that is, Vb11 is used as the pre-charge voltage of the red sub-pixel R12).
Claim 4 (Currently Amended),
HUANG et al. teach
the array substrate according to claim 1, wherein a same data line ([0053], FIG. 2, i.e. data line DA1) is connected with the plurality of groups of sub-pixels (FIG. 2, i.e. subgroups including R11, R21, R31, … , R61, R71 as shown by the figure(s)), and a plurality of sub-pixels corresponding to a same color (FIG. 2, i.e. red as R11, R31, … , R51, R71 as shown by the figure(s)) and connected with the same data line ([0053], FIG. 2, i.e. data line DA1) are connected with odd rows ([0062], FIG. 2, i.e. GA1, GA5, GA9, and GA13) of gate lines or even rows of gate lines (i.e. alternative limitation(s) omitted).
Claim 5 (Original),
HUANG et al. teach
the array substrate according to claim 4, wherein sub-pixels in a same column ([0058], FIG. 2, i.e. first (odd) column as shown by the figure(s)) correspond to a same color (FIG. 2, i.e. red as shown by the figure(s)), a plurality of sub-pixels corresponding to red (FIG. 2, i.e. red as R11, R31, R51, R71 as shown by the figure(s)) are connected with the odd rows (FIG. 2, i.e. odd rows GA1, GA5, GA9, GA13 as shown by the figure(s)) of gate lines, a plurality of sub-pixels corresponding to green (FIG. 2, i.e. green as G11, G31, G51, G71 as shown by the figure(s)) are connected with the even rows (FIG. 2, i.e. even rows GA2, GA6, GA10, and GA14 as shown by the figure(s)) of gate lines, and a plurality of sub-pixels corresponding to blue (FIG. 2, i.e. blue as B11, B31, B51, and B71 as shown by the figure(s)) and connected with the same data line ([0053], FIG. 2, i.e. data line DA1) are connected with a plurality of odd rows ([0062], FIG. 2, i.e. GA1, GA5, GA9, GA13) of gate lines or a plurality of even rows of gate lines (i.e. alternative limitation(s) omitted); or
a plurality of sub-pixels corresponding to green are connected with the odd rows of gate lines, a plurality of sub-pixels corresponding to blue are connected with the even rows of gate lines, and a plurality of sub-pixels corresponding to red and connected with the same data line are connected with a plurality of odd rows of gate lines or a plurality of even rows of gate lines (i.e. alternative limitation(s) omitted); or
a plurality of sub-pixels corresponding to red are connected with the odd rows of gate lines, a plurality of sub-pixels corresponding to blue are connected with the even rows of gate lines, and a plurality of sub-pixels corresponding to green and connected with the same data line are connected with a plurality of odd rows of gate lines or a plurality of even rows of gate lines (i.e. alternative limitation(s) omitted).
Claim 6 (Original),
HUANG et al. teach
the array substrate according to claim 4, wherein sub-pixels in a same column (FIG. 2, i.e. first column, second column, and third column as shown by the figure(s)) correspond to a same color (FIG. 2, i.e. red, green, and blue correspondingly as shown by the figure(s)), a plurality of sub-pixels corresponding to red (FIG. 2, i.e. red as R11, R31, R51, and R71 as shown by the figure(s)) and connected with the same data line ([0053], FIG. 2, i.e. data line DA1) are connected with a plurality of odd rows (FIG. 2, i.e. odd rows first, fifth, nineth, and thirteenth as shown by the figure(s)) of gate lines ([0062], FIG. 2, i.e. GA1, GA5, GA9, and GA13) or a plurality of even rows of gate lines (i.e. alternative limitation(s) omitted), a plurality of sub-pixels corresponding to green (FIG. 2, i.e. green as G12, G32, G52, G72 as shown by the figure(s)) and connected with the same data line ([0053], FIG. 2, i.e. data line DA2) are connected with a plurality of odd rows ([0062], FIG. 2, i.e. GA1, GA5, GA9, GA13) of gate lines or a plurality of even rows of gate lines (i.e. alternative limitation(s) omitted), and a plurality of sub-pixels corresponding to blue (FIG. 2, i.e. blue as B11, R31, R51, R71 as shown by the figure(s)) and connected with the same data line ([0053], FIG. 2, i.e. data line DA1) are connected with a plurality of odd rows ([0062], FIG. 2, i.e. GA1, GA5, GA9, GA13) of gate lines or a plurality of even rows of gate lines (i.e. alternative limitation(s) omitted).
Claim 12 (Original),
HUANG et al. teach
a driving method ([0004], FIG. 2, i.e. method for driving a display panel), applied to the array substrate according to claim 1, wherein the method (i.e. alternative limitation(s) omitted) comprises, turning on ([0051], FIG. 2, i.e. driving … to control the connected transistors to be turned on) a plurality of gate lines ([0051], FIG. 2, i.e. driving the gate lines GA1, GA2, GA3, . . . GA13, GA14) connected with each group of sub-pixels (i.e. please see above citation(s)); and
charging ([0051], FIG. 2, i.e. to charge the sub-pixels), during a period ([0062], FIG. 4, i.e. display frame F1) when the plurality of gate lines of each group of sub-pixels are turned on (i.e. please see above citation(s)), each group of sub-pixels by the plurality of data lines ([0051], FIG. 2, i.e. plurality of data lines (for example, DA1, DA2, DA3, DA4, DA5)).
Claim 16 (Currently Amended),
the method according to claim 12, wherein the charging time of the first part of the plurality of rows of sub-pixels is a charging time ([0062], FIG. 2, i.e. time period T11) of one row ([0062], FIG. 2, i.e. gate line GA1) of sub-pixels, the charging time of the second part of the plurality of rows of sub-pixels (i.e. please see above citation(s)) is a charging time ([0062], FIG. 2, i.e. time period T11 corresponding to the high level of the signal ga1 … the time period T11, the signal ga2 on the second gate line GA2 outputs a high-level gate-on signal) of two rows of sub-pixels ([0062], FIG. 2, i.e. time period T11 corresponding to the high level of the signal ga1 … the time period T11, the signal ga2 on the second gate line GA2 outputs a high-level gate-on signal), and the first part ([0062], FIG. 2 &4, i.e. “data voltage Vb11” of ga1 as shown by the figure(s)) of the plurality of rows of sub-pixels (i.e. please see above citation(s)) and the second part ([0062], FIG. 2 &4, i.e. “data voltage Vb11” of ga2 as shown by the figure(s)) of the plurality of rows of sub-pixels (i.e. please see above citation(s)) start being charged simultaneously ([0062], FIG. 2 &4, i.e. data voltage Vb11 is simultaneously input into the red sub-pixel R12 to pre-charge the red sub-pixel R12, that is, Vb11 is used as the pre-charge voltage of the red sub-pixel R12).
Claim 17 (Currently Amended),
HUANG et al. teach
a display device ([0051], FIG. 1, i.e. display panel 100), comprising the array substrate according to claim 1 (i.e. please see above citation(s)).
Claim 19 (Currently Amended),
HUANG et al. teach
the display device according to claim 17, further comprising a circuit board ([0051], FIG. 1, i.e. timing controller 300), wherein the circuit board (i.e. please see above citation(s)) is provided with a timing controller ([0051], FIG. 1, i.e. timing controller 300), and the array substrate (i.e. please see above citation(s)) further comprises a source driver chip ([0051], FIG. 1, i.e. source driving circuit 120), wherein the timing controller (i.e. please see above citation(s)) is coupled with (FIG. 1, i.e. as shown by the figure(s)) the source driver chip (i.e. please see above citation(s)) and configured to provide display data ([0051], FIG. 1, i.e. inputs a signal) to the source driver chip; and
the source driver chip (i.e. please see above citation(s)) is coupled with (FIG. 1, i.e. as shown by the figure(s)) the plurality of data lines (i.e. please see above citation(s)) and configured to provide data signals ([0051], FIG. 1, i.e. to make the source driving circuit 120 input a voltage to the data lines) to the plurality of data lines (i.e. please see above citation(s)) according to the display data ([0051], FIG. 1, i.e. to realize the display function).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over HUANG et al. (US Patent/PGPub. No. 20240355258) in view of Hao (US Patent/PGPub. No. 20180181239).
Claim 18 (Original),
HUANG et al. teach
the display device according to claim 17.
However, HUANG et al. do not explicitly teach
further comprising a counter substrate, wherein the counter substrate comprises a color filter layer, the color filter layer comprises a plurality of color filters, the plurality of color filters comprise a plurality of blue color filters, a plurality of red color filters and a plurality of green color filters, and the plurality of color filters are in one-to-one correspondence with the plurality of rows and the plurality of columns of sub-pixels.
In the same field of endeavor, Hao teaches
further comprising a counter substrate ([0011], FIG. 14-15, i.e. color filter substrate which are arranged oppositely), wherein the counter substrate (i.e. please see above citation(s)) comprises a color filter layer ([0011], FIG. 14-15, i.e. color filter substrate), the color filter layer comprises a plurality of color filters ([0046], FIG. 14-15, i.e. a red (R) color filter, a green (G) color filter and a blue (B) color filter), the plurality of color filters comprise a plurality of blue color filters ([0046], FIG. 14-15, i.e. a blue (B) color filter), a plurality of red color filters ([0046], FIG. 14-15, i.e. a red (R) color filter) and a plurality of green color filters ([0046], FIG. 14-15, i.e. a green (G) color filter), and the plurality of color filters are in one-to-one correspondence with the plurality of rows and the plurality of columns of sub-pixels ([0046], FIG. 14-15, i.e. Each pixel unit 10 comprises three sub-pixel units that are corresponding to a red (R) color filter, a green (G) color filter and a blue (B) color filter).
It would have been obvious to a person having ordinary skill in the art at the time the invention’s effective date was filed to combine HUANG et al. teaching of a display comprising plurality of sub-pixels with Hao teaching of a display comprising plurality of color filters corresponding to each sub-pixels to effectively display any color utilizing the three basic colors of red, green, and blue (Hao’s [0003]).
4. Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over HUANG et al. (US Patent/PGPub. No. 20240355258) in view of MA et al. (US Patent/PGPub. No. 20180181239).
Claim 20 (Original),
HUANG et al. teach
the display device according to claim 19, wherein the circuit board (i.e. please see above citation(s)) further comprises a level conversion unit ([0051], FIG. 1, i.e. level shift circuit 200), and the array substrate further comprises a gate driving circuit ([0051], FIG. 1, i.e. gate driving circuit 110), the level conversion unit is coupled with (FIG. 1, i.e. as shown by the figure(s)) the timing controller, the gate driving circuit (i.e. please see above citation(s)) is connected with (FIG. 1, i.e. as shown by the figure(s)) the level conversion unit and the plurality of gate lines(i.e. please see above citation(s)).
However, HUANG et al. do not explicitly teach
the level conversion unit is configured to receive a plurality of first clock signals provided by the timing controller, convert the plurality of first clock signals into a plurality of second clock signals, and provide the plurality of second clock signals to the gate driving circuit, and the gate driving circuit is configured to provide gate signals to the plurality of gate lines according to the plurality of second clock signals, so as to control the plurality of gate lines to be turned on.
In the same field of endeavor, MA et al. teach
the level conversion unit ([0120], FIG. 5, i.e. level conversion unit 502) is configured to receive a plurality of first clock signals ([0120], FIG. 5, i.e. the timing controller 501 … to provide a first clock signal to the level conversion unit 502) provided by the timing controller ([0120], FIG. 5, i.e. timing controller 501), convert the plurality of first clock signals into a plurality of second clock signals ([0003], FIG. 5, i.e. level conversion unit is configured to convert a plurality of first clock signals received by the plurality of first clock signal input terminals into a plurality of second clock signals), and provide the plurality of second clock signals to the gate driving circuit ([0003], FIG. 5, i.e. gate electrode driving unit; [0121], FIG. 5, i.e. gate electrode driving unit 503), and the gate driving circuit is configured to provide gate signals to the plurality of gate lines ([0003], FIG. 5, i.e. gate electrode driving unit is configured to sequentially shift and output a plurality of first gate scan signals by a first portion of the 2n gate signal output terminals) according to the plurality of second clock signals (i.e. please see above citation(s)), so as to control the plurality of gate lines to be turned on ([0002], FIG. 5, i.e. so as to control the plurality of rows of gate lines to be sequentially turned on).
It would have been obvious to a person having ordinary skill in the art at the time the invention’s effective date was filed to realize HUANG et al. teaching of a display comprising timing controller and level conversion unit would have included shifting first signals to second signals as disclosed by MA et al. teaching of a display comprising timing controller and level conversion unit shifting signals to effectively provide required voltage for each grayscale of a display image in each pixel unit (MA et al.’s [0002] both teachings disclosed similar features to accomplish similar functions).
Allowable Subject Matter
5. Claim(s) 7-11 and 13-15 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
6. The following is an examiner’s statement of reasons for allowance:
HUANG et al. (US Patent/PGPub. No. 20240355258) teach a method for driving a display panel, and a display apparatus. An example of the method includes: receiving display data of an image to be displayed of the current display frame; and according to the display data, controlling a display panel to sequentially load a gate-on signal to gate lines, and to input a voltage into a data line, and when there is an overlap time between gate-on signals loaded to M adjacent gate lines, a pre-charging voltage and a compensation voltage are sequentially charged to a sub-pixel electrically connected to an Mth gate line among the M gate lines within the overlap time, M being an integer and M≥2
Hao (US Patent/PGPub. No. 20180181239) teaches a liquid crystal display device having a touch sensor and a method of driving the same, which relates to the technical field of liquid crystal display. The liquid crystal display device having a touch sensor is provided to solve the problem that a penetration rate of a display device in the prior art is decreased significantly. A touch control function is added in a pixel of the liquid crystal display device and the touch control function is achieved through a touch lead. Common electrodes covering data lines between blue sub-pixels and red sub-pixels of two adjacent pixel units are set as touch leads. The touch leads serve as touch lines during a touch scanning stage and serve as the common electrodes during a non-touch scanning stage. Moreover, the present disclosure is mainly applied to a liquid crystal flat display panel.
The subject matter of the independent claims could either not be found or was not suggested in the prior art of record. The subject matter not found was a display device including
“…wherein an image frame comprises a first display period and a second display period, two adjacent odd rows of gate lines are taken as a group, two adjacent even rows of gate lines are taken as a group, and two rows of sub-pixels connected with each group of gate lines are taken as a group of sub-pixels,
for odd rows of gate lines, a plurality of groups of odd rows of gate lines are sequentially turned on during the first display period; and
for even rows of gate lines, a plurality of groups of even rows of gate lines are sequentially turned on during the second display period,
wherein, in each group of gate lines, a gate line connected with the first part of the plurality of rows of sub-pixels is turned on earlier than a gate line connected with the second part of the plurality of rows of sub-pixels.” (Claim 7),
“…wherein two gate lines are taken as a gate line group, two rows of sub-pixels respectively connected with the two gate lines in the gate line group form a sub-pixel group, and sub-pixels connected with the same data line in the sub-pixel group correspond to a same color; and
a plurality of groups of gate lines are sequentially turned on, wherein for each group of gate lines, a gate line connected with the first part of the plurality of rows of sub-pixels is turned on earlier than a gate line connected with the second part of the plurality of rows of sub-pixels.” (Claim 8),
“…wherein the plurality of gate lines comprise a plurality of first gate line groups, the plurality of groups of sub-pixels comprise a plurality of first sub-pixel groups, each first gate line group comprises two adjacent gate lines, two rows of sub-pixels connected with each first gate line group form the first sub-pixel group, and two sub-pixels connected with a same data line in each first sub-pixel group correspond to a same color.” (Claim 9),
“…wherein a same data line is connected with the plurality of groups of sub-pixels, a plurality of sub-pixels having a same luminous color and connected with the same data line are connected with odd rows of gate lines or even rows of gate lines, an image frame comprises a first display period and a second display period, two adjacent odd rows of gate lines are taken as a group, two adjacent even rows of gate lines are taken as a group, and two rows of sub-pixels connected with each group of gate lines are taken as a group of sub-pixels;
wherein the turning on the plurality of gate lines connected with each group of sub- pixels sequentially comprises:
during the first display period, turning on the odd rows of gate lines sequentially;
during the second display period, turning on the even rows of gate lines sequentially,
wherein, in each group of gate lines, a gate line connected with the first part of the plurality of rows of sub-pixels is turned on earlier than a gate line connected with the second part of the plurality of rows of sub-pixels.” (Claim 13),
“…wherein two gate lines are taken as a gate line group, two rows of sub-pixels respectively connected with the two gate lines in the gate line group form a sub-pixel group, and sub-pixels connected with the same data line in the sub-pixel group correspond to a same color,
wherein the turning on the plurality of gate lines connected with each group of sub-pixels comprises:
turning on a plurality of groups of gate lines sequentially, wherein, for each group of gate lines, a gate line connected with the first part of the plurality of rows of sub-pixels is turned on earlier than a gate line connected with the second part of the plurality of rows of sub-pixels.” (Claim 14),
“…wherein the plurality of gate lines comprise a plurality of first gate line groups, each group of sub-pixels comprises two adjacent rows of sub-pixels, each first gate line group comprises two adjacent gate lines, the plurality of groups of sub-pixels comprise a plurality of first sub-pixel groups, and two sub-pixels connected with a same data line in each first sub-pixel group correspond to a same color,
wherein the turning on the plurality of gate lines connected with each group of sub- pixels sequentially comprises,
turning on each gate line sequentially, wherein a gate line connected with the first part of the plurality of rows of sub-pixels is turned on earlier than a gate line connected with the second part of the plurality of rows of sub-pixels.” (Claim 15),
in combination with the other elements (or steps) of the device or apparatus and method recited in the claims.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINH TANG LAM whose telephone number is (571) 270-3704. The examiner can normally be reached Monday to Friday 8:00 AM to 5:00 PM.
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/VINH T LAM/Primary Examiner, Art Unit 2628