DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-9, 11, 13, 15-16, 18, 20-21, 25-26, 28 and 30 are pending in the application.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement(s) (IDS), Form PTO-1449, filed 30 December 2024. The information therein was considered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xu et al. (US 2023/0052091) (hereinafter, “Xu”).
Re: independent claim 1, Xu discloses in figs. 1-7 an array substrate having a display area (DA) and a first frame area (NA) arranged in a first direction; the first frame area (NA) including a chip setting area (CA) and bonding areas (including 130); in a second direction, the bonding areas (130) being located on at least one side of the chip setting area (CA); the second direction intersecting the first direction; the array substrate comprising: a plurality of driving pads (121, 181) disposed in the chip setting area (CA); a plurality of bonding pins (131) disposed in a bonding area (130); and a plurality of peripheral connection lines (140) disposed in the first frame area; an end of each peripheral connection line (140) being connected to a driving pad (121, 181), and another end of each peripheral connection line (140) being connected to a bonding pin (131), wherein the plurality of peripheral connection lines (140) include first peripheral connection lines (140), the first peripheral connection lines (140) extend to a side of the chip setting area (CA) proximate to the bonding area (130) in the chip setting area; an end of a first peripheral connection line (140) is connected to a driving pad (121, 181) in the chip setting area (CA), and another end of the first peripheral connection line (140) is connected to a bonding pin (131) in the bonding area (130).
Re: claim 2, Xu discloses in figs. 1-7 the array substrate according to claim 1, wherein the plurality of driving pads are arranged into a plurality of driving pad groups, and the plurality of driving pad groups include: an output pad group (180) including a plurality of output pads (181) arranged in the second direction; and an input pad group (120) including a plurality of input pads (121) arranged in the second direction, wherein the input pad group (120) is located on a side of the output pad group (180) away from the display area (DA); the first peripheral connection lines (140) extend to the side of the chip setting area (CA) proximate to the bonding area (130) between the input pad group (120) and the output pad group (180); the driving pad (121, 181) connected to the end of the first peripheral connection line (140) is an input pad (121), the end of the first peripheral connection line (140) is connected to an end of the input pad (121) proximate to the output pad group (181), and the another end of the first peripheral connection line (140) is connected to an end of the bonding pin (131) proximate to the display area (DA).
Re: claim 3, Xu discloses in figs. 1-7 the array substrate according to claim 2, wherein the plurality of peripheral connection lines further include: second peripheral connection lines (140), wherein the second peripheral connection lines (140) extend to the side of the chip setting area (CA) proximate to the bonding area (130) at a side of the chip setting area (CA) away from the display area (DA); a driving pad connected to an end of a second peripheral connection line (140) is another input pad (121), the end of the second peripheral connection line (140) is connected to an end of the another input pad (121) away from the output pad group (180), and another end of the second peripheral connection line (140) is connected to an end of another bonding pin (131) in the bonding area (130) proximate to the display area (DA).
Re: claim 4, Xu discloses in figs. 1-7 the array substrate according to claim 3, wherein the bonding pin (131) connected to the first peripheral connection line (140) is a first bonding pin (131a); the another bonding pin (131b) connected to the second peripheral connection line (140) is a second bonding pin; the first bonding pin (131a) is farther away from the chip setting area (CA) than the second bonding pin (131b), and the second peripheral connection line (140) is located at a side of the first peripheral connection line (140) away from of the display area (DA).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xu et al. (US 2023/0052091) (hereinafter, “Xu”) in view of Yu et al. (CN113380656) (hereinafter, “Yu”).
Re: claim 25, Xu discloses in figs. 1-7 the array substrate according to claim 1.
Xu does not disclose an array motherboard having a plurality of product areas and a plurality of areas to be cut, and every two adjacent product areas having an area to be cut therebetween; and the array substrate being located in a product area.
Yu discloses in fig. 4 an array motherboard having a plurality of product areas (MM) and a plurality of areas to be cut (NN), and every two adjacent product areas having an area to be cut therebetween; and the array substrate being located in a product area.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to separate a plurality product area by cutting for the purpose of obtaining individual display devices as exemplified by Yu.
Allowable Subject Matter
Claims 5-9, 11, 13, 15-16, 18, 20-21, 26, 28 and 30 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. When responding to this office action, applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
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/ALLISON BERNSTEIN/Primary Examiner, Art Unit 2824 9/18/2026
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