Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
The applicant’s claim of the benefit of and priority to PCT Provisional Application No. PCT/CN2022/083264, filed March 28, 2022, is granted. Priority to International Application No. PCT/US2022/077172, filed September 28, 2022 is not granted as no certified copy of the priority document has been received.
Response to Amendment
This Office Action is in response to the amendments filed September 15, 2025.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 21, 23, 26, 28, 31, and 33 are rejected under 35 U.S.C. 102 as being anticipated by Nakajima et al. (U.S. patent application publication 20160048464 A1), hereinafter referred to as Nakajima.
Regarding claims 21 and 26, Nakajima discloses An apparatus (Nakajima computing device 100) comprising: processing circuitry to: “computing device 100 includes the processor 120” [Nakajima paragraph 19] configure access permissions relating to a secure buffer to allow one or more user entities to access the secure buffer, wherein the one or more user entities include one or more virtual machines; (“The target virtual machine may access the shared memory by switching to the secure view EPT using virtualization support of the processor 120 and then executing normal memory accesses to the shared memory segment” [Nakajima paragraph 17]. Furthermore “generating, by the source virtual machine, a shared buffer to be processed by the target computing device, wherein the second shared memory segment includes the shared buffer; processing, by the target virtual machine, the shared buffer in response to accessing the shared memory segment; and coordinating, by the target virtual machine and the source virtual machine, ownership of the shared buffer using a secure view control structure stored in the shared memory segment established by the virtual machine monitor” [Nakajima paragraph 108]. Wherein a buffer as well as a memory segment, each requiring a secure view to access, would both be examples of a secure buffer, and the processor enables the secure view which provides access permission to virtual machines) allocate memory space to the secure buffer; and (“the computing device 100 reclaims each used buffer 404. For example, the source virtual machine 206 may free, delete, or otherwise deallocate memory associated with each buffer 404 within the used region 718” [Nakajima paragraph 77]. Wherein the buffer 404 is in the memory, and for memory to be deallocated, the memory must have been previously allocated. Therefore the apparatus of Nakajima is configured to perform the allocation of memory space) allow secure access to the secure buffer to the one or more user entities in response to successfully verifying the one or more user entities (“the computing device comprising: an authentication module to authenticate, by a virtual machine monitor of the computing device, a view switch component of a target virtual machine of the computing device in response to a request to authenticate the view switch component received from the target virtual machine; a secure view module to configure, by the virtual machine monitor in response to authentication of the view switch component, a secure memory view to access a shared memory segment of the computing device in response to a request to access the shared memory segment received from the target virtual machine” [Nakajima claim 1]. Wherein authenticating is verifying) and authorizing the one or more user entities to access the secure buffer (authorizing access is synonymous with allowing access in response to verification, therefore this claim limitation is rejected under the same rationale as the previous claim limitation above).
Regarding claim 31, it is rejected under the same rationale as claim 21 above, with the additional rationale that Nakajima discloses At least one computer-readable medium having stored thereon instructions which, when executed, cause a computing device to perform operations (“The disclosed embodiments may also be implemented as instructions carried by or stored on a transitory or non-transitory machine-readable (e.g., computer-readable) storage medium, which may be read and executed by one or more processors” [Nakajima paragraph 15]).
Regarding claims 23, 28, and 33, Nakajima discloses The apparatus of claim 21, wherein the processing circuitry is further to control the secure buffer, wherein to control includes creating the secure buffer, (“generating, by the source virtual machine, a shared buffer” [Nakajima paragraph 108]) deleting the secure buffer, (“removing, by the source virtual machine, the shared buffer from the grant table in response to the target virtual machine completing processing of the shared buffer; reclaiming, by the source virtual machine, the shared buffer in response to removing the shared buffer from the grant table; and invalidating, by the virtual machine monitor, an extended page table of the computing device in response to reclaiming the shared buffer” [Nakajima paragraph 109]) and setting ((Setting: “In block 906, the computing device 100 adds the newly-created shared buffer to the grant table 232. As described above, adding the buffer to the grant table 232 indicates that the buffer should be shared with the target virtual machine 204. In block 908, the computing device 100 sends a request to the VMM 202 to share the new buffer with the target virtual machine 204” [Nakajima paragraph 74]. Wherein granting shared access to the buffer would be setting an access permission)) and revoking the access permissions to the secure buffer (“After all in-use buffers 404 are processed, in block 916 the computing device 100 removes each used buffer 404 from the grant table 232. As described above, by removing those buffers 404 from the grant table 232, the source virtual machine 206 indicates that those buffers should no longer be shared with the target virtual machine 204” [Nakajima paragraph 77]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 22, 24, 27, 29, 32, and 34 are rejected under 35 U.S.C. 103 as being unpatentable over Nakajima, in view of Liu et al. (U.S. patent application publication 20220066809 A1), hereinafter referred to as Liu.
Regarding claims 22, 27, and 32, Nakajima teaches The apparatus of claim 21, wherein the processing circuitry is further to create the secure buffer (“In block 904, the computing device 100 produces a new shared buffer” [Nakajima paragraph 73]) and assign ownership of the secure buffer to a secure buffer owner, (“In block 904, the computing device 100 produces a new shared buffer to be shared with the target virtual machine 204.” [Nakajima paragraph 73]. Additionally, “The target virtual machine and the source virtual machine may coordinate ownership of memory pages using a secure view control structure stored in the shared memory segment” [Nakajima abstract]. Wherein the memory pages would comprise the memory segment that serves as the secure buffer and a virtual machine assigned ownership of the memory pages would be a secure buffer owner) wherein the secure buffer is securely shared by multiple users, (“In block 306, the computing device 100 determines whether additional virtual machines 204, 206 should have view switch components 226 authenticated. For example, multiple target virtual machines 204 may request authentication to access shared memory. As another example, both a target virtual machine 204 and a source virtual machine 206 may request authentication to communication over a secure channel using the shared memory segment 214” [Nakajima paragraph 37; Fig. 3]).
Nakajima does not appear to explicitly disclose wherein the one or more virtual machines include one or more trusted execution environment (TEE)-based virtual machines.
However, Liu teaches wherein the one or more virtual machines include one or more trusted execution environment (TEE)-based virtual machines (“in response to that a logical processor running on a physical processor core generates a trusted execution environment entry event through an approach provided by a virtual machine monitor” [Liu abstract] which describes a hypervisor overseeing a VM being added to a TEE).
Nakajima and Liu are analogous art because they are from the same field of endeavor of computer memory security.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Nakajima and Liu before him or her, to modify the apparatus of Nakajima to include the attributes of wherein the one or more virtual machines include one or more trusted execution environment (TEE)-based virtual machines of Liu because it will enhance apparatus security.
The motivation for doing so would be “Trusted execution environments (TEEs) can play a role of a black box in hardware. Neither code nor data executed in the TEEs can be snooped by an operating system layer” [Liu paragraph 2]. Thus implementing the TEE would improve security.
Therefore, it would have been obvious to combine Nakajima and Liu to obtain the invention as specified in the instant claim.
Regarding claims 24, 29, and 34 Nakajima/Liu teach The apparatus of claim 21, wherein the secure buffer owner and the one or more user entities relate to one or more trusted domains (TDs), (The instant application recites “trusted execution environment (TEE) virtual machines (VMs)(TVMs). In some implementations, TVMs are called trusted domains (TDs)" (paragraph 3). Therefore the TEE-based virtual machines of Liu (see the rejection to claim 2 above) would be TDs as defined by the specification of the instant application) wherein the one or more TDs are configured to verify and authorize the one or more user entities (verifying and authorizing the one or more user entities is taught by Nakajima [see the rejection to claim 21 above]. It would have been obvious to a person having ordinary skill in the art to combine that functionality with the TDs of Liu because it would allow users to securely access a domain. For example, a TD owner would be able to vet user access to the TD, instead of delegating authority to the processing circuitry, thus enhancing security).
Claims 25, 30, and 35 are rejected under 35 U.S.C. 103 as being unpatentable over Nakajima in view of Durham et al. (U.S. patent application publication 20190042764 A1), hereinafter referred to as Durham.
Regarding claims 25, 30, and 35 Nakajima teaches The apparatus of claim 21, wherein the secure buffer comprises a selected set of host physical address pages (“EPT support 124 provides hardware-assisted translation between guest-physical memory addresses to physical memory addresses (also known as host-physical memory addresses)” [Nakajima paragraph 21]. Furthermore, “Example 3 includes the subject matter of any of Examples 1 and 2, and wherein the shared memory segment comprises one or more physical memory pages of the computing device” [Nakajima paragraph 81]. Wherein a segment is a single section of something, thus a memory segment comprising one or more physical memory pages would be a single continuous grouping of memory pages. Sharing a specific segment of memory would intrinsically include selecting that segment of memory for sharing) allocated from a private guest physical address space relating to the secure buffer owner, (Nakajima Fig. 7 depicts buffers in a guest physical address space. The allocation can also be seen in the figure. The address space is related to the secure buffer owner because the memory space for the buffers is being shared with the owner) wherein the processing circuitry is coupled to a memory, (Nakajima Fig. 1; processor 120 is depicted coupled to memory 130) the processing circuitry including one or more of application processing circuitry or graphics processing circuitry (“the processor 120 supports hardware-assisted translation between virtual memory addresses (used, for example, by applications executing within a guest VM)” [Nakajima paragraph 21]).
Nakajima does not appear to explicitly disclose and wherein the one or more user entities share a key domain with the secure buffer owner.
However, Durham teaches and wherein the one or more user entities share a key domain with the secure buffer owner (see Fig. 3 Key Domain KD1 350 and memory ownership table 380. This demonstrates multiple entities sharing a key domain, with at least one of the entities having ownership of memory, making it a secure buffer owner).
Nakajima and Durham are analogous art because they are from the same field of endeavor of computer memory security.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Nakajima and Durham before him or her, to modify the apparatus of Nakajima to include the attributes of wherein the one or more user entities share a key domain with the secure buffer owner of Durham because it will enhance apparatus security.
The motivation for doing so would be that with the key domains in the apparatus of Durham, “The host VMM may determine the associated key identifier (KeyID) for the key domain. The host VMM has access only to the encrypted key domain key and therefore cannot decrypt the guest VM's protected key domain.” This eliminates a possible attack vector, enhancing apparatus security.
Therefore, it would have been obvious to combine Nakajima and Durham to obtain the invention as specified in the instant claim.
Response to Arguments
Examiner thanks the applicant for their remarks of September 15, 2025. The remarks have been accepted and fully considered, but the arguments regarding 35 USC § 102 and 103 are not persuasive.
In light of the amendments to the claims, all claim objections and 112(b) rejections are withdrawn.
On page 7 of the applicant’s remarks, applicant recites “Nakajima is an old reference, dating back to 2014 that merely relates to an archaic technique”. In response to applicant's argument based upon the age of the references, contentions that the reference patents are old are not impressive absent a showing that the art tried and failed to solve the same problem notwithstanding its presumed knowledge of the references. See In re Wright, 569 F.2d 1124, 193 USPQ 332 (CCPA 1977).
Also on page 7, applicant recites “Nakajima’s technique … does not anticipate the elements of claim 21”. The examiner disagrees. Under the broadest reasonable interpretation of claim 21, Nakajima does anticipate the elements of claim 21. The applicant is directed to the rationale provided in the rejection to claim 21 above.
On page 8 of the applicant’s remarks, applicant recites that claims 22-35 are allowable either for the same reasons as claim 21 or because they depend on a claim that is allowable for the same reasons as claim 21. This argument is moot because claim 21 is not allowable.
Pertinent Prior art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20210406054 A1 – Tsirkin et al.
Relevant excerpt: “Providing virtual devices implemented in the hypervisor access to guest memory of a VM poses an inherent security issue. For example, confidential data of the guest VM may be vulnerable to snooping by unauthorized users or software (e.g., using hardware probing). SEV addresses this by allowing VMs to designate certain pages of guest memory as encrypted (private) and other pages of guest memory as unencrypted (shared). Guest memory pages designated as shared may be used for communication between a VM and the hypervisor as well as virtual devices executing on the hypervisor, for example. Guest memory pages designated as private are encrypted using an encryption key assigned to the VM and are for the exclusive use of the VM for storing confidential data.” [paragraph 11]
US 20190042476 A1 – Chhabra et al.
Relevant excerpt: “Techniques are described for providing low-overhead cryptographic memory isolation to mitigate attack vulnerabilities in a multi-user virtualized computing environment. Memory read and memory write operations for target data, each operation initiated via an instruction associated with a particular virtual machine (VM), include the generation and/or validation of a message authentication code that is based at least on a VM-specific cryptographic key and a physical memory address of the target data. Such operations may further include transmitting the generated message authentication code via a plurality of ancillary bits incorporated within a data line that includes the target data. In the event of a validation failure, one or more error codes may be generated and provided to distinct trust domain architecture entities based on an operating mode of the associated virtual machine.” [abstract]
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/C.J.O./
Examiner, Art Unit 2138
/Kaushikkumar M Patel/Primary Examiner, Art Unit 2138
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