DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Amendment
Applicant’s amendment filed on June 22, 2026 has been entered. Claims 1, 8, and 24-26 have been amended. Claims 5-7, 9-13, 18, 20, and 28-29 have been cancelled. Claims 1-4, 8, 14-17, 19, 21-27 and 30 are pending in this application.
Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claim(s) 1-4, 8, 16-17 and 21-25 are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al. (US 2023/0154403) in view of Zhang et al. (US 2019/0051238),
Regarding claim 1, Kang discloses a display substrate (Figs 1 and 7; [0065], [0250], e.g., a display substrate 1000), comprising:
a base substrate (Fig. 7, [0254], e.g., base substrate SUB) and a drive circuit layer ([0254], e.g., pixel circuit layer PCL) disposed on the base substrate, wherein the drive circuit layer comprises at least a plurality of circuit units, at least one of the plurality of circuit units comprises a pixel circuit (Figs 2A and 7; e.g., the pixel circuit layer PCL comprises a plurality of pixel circuits PX), and the pixel circuit (Fig. 2A, [0110], e.g., PX) comprises at least a first capacitor (e.g., C1), a second capacitor (e.g., C2), a data writing transistor (e.g., T2), a drive transistor (e.g., T1), and a first light emitting control transistor (e.g., T6);
a first end of the first capacitor is electrically connected with a gate electrode of the drive transistor ([0113], e.g., a first end N1 of C1 is connected with a gate electrode of T1), a second end of the first capacitor is electrically connected with a second end of the second capacitor (e.g., a second end N3 of C1 is connected with a second end N3 of C2), and a first end of the second capacitor is electrically connected with a first signal line ([0114], e.g., a first signal line VDD);
a gate electrode of the data writing transistor is electrically connected with a third scan signal line ([0115], e.g., a gate electrode of T2 is connected with a third scan signal line SL1i), a first electrode of the data writing transistor is electrically connected with a data signal line (e.g., data signal line DLj), and a second electrode of the data writing transistor is electrically connected with the second end of the first capacitor and the second end of the second capacitor (e.g., the second end N3 of C1 and the second end N3 of C2);
a gate electrode of the first light emitting control transistor is electrically connected with a first light emitting signal line ([0120], e.g., a gate electrode of T6 is connected with a first light emitting signal line EL1i), a first electrode of the first light emitting control transistor is electrically connected with a first power supply line (e.g., a first power supply line VDD), and a second electrode of the first light emitting control transistor is electrically connected with a first electrode of the drive transistor (e.g., a second electrode of T6 is connected with a first electrode of T1);
the first power supply line extends along a second direction (Figs 6A and 6F; [0248], e.g., first power supply line VL_VDD extends along a second direction DR1), and the drive circuit layer further comprises at least one first power supply connection line extending along a first direction ([0247]-[0248], e.g., first power supply connection line VDDL is extending along a first direction DR2), the first direction intersecting with the second direction (e.g., the first direction Dr1 intersects with the second direction DR2); the first power supply line is connected with the first power supply connection line to form a meshe structure for transmitting a first power supply signal ([0248], e.g., the power source line VL_VDD connected to the first power supply connection line VDDL through the third bridge pattern BRP3 and a contact hole may extend in the first direction DR1 and thus may have a mesh structure); and
the drive circuit layer further comprises at least one second power supply connection line extending along the first direction (Figs 6A-6F; [0243], at least one second power supply connection line VREFL extending along the first direction DR2) and at least one second power supply line extending along the second direction ([0246], e.g., at least one second power supply line VL_REF extending along the second direction DR1), the second power supply line is connected with the second power supply connection line to form a mesh structure for transmitting a second power supply signa ([0248], e.g., the second power supply line VL_REF is connected with the second power supply connection line VREFL to form a mesh structure for transmitting a second power supply signal VREF); and
the second power supply connection line is located at a side of the first power supply connection line close to the second capacitor (e.g., the second power supply connection line VREFL is located at a side of the first power supply connection line VDDL close to the second capacitor C2_E1).
Kang does not specifically disclose wherein the first signal line and the first power supply line are configured to provide different constant voltage signals.
However, Zhang discloses a pixel circuit (Fig. 4; [0045]) comprising: at least a first capacitor ([0047], e.g., C2), a second capacitor (e.g., C1), a data writing transistor ([0046], e.g., M4), a drive transistor ([0047], e.g., M3), and a first light emitting control transistor ([0048], e.g., M6),
wherein a first end of the second capacitor is electrically connected with a first signal line ([0045], e.g., Vin);
a first electrode of the drive transistor is electrically connected with a first power supply line (e.g., VDD); and
wherein the first signal line and the first power supply line are configured to provide different constant voltage signals ([0045], e.g., a voltage level of the initializing signal outputted from the initializing signal terminal Vin is always a first voltage level and a voltage level of the first power source signal outputted from the first power source signal terminal VDD is always a second voltage level).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the teachings of Zhang in the invention of Kang for electrically connecting a first end of the second capacitor is electrically connected with a first signal line and providing different constant voltage signals for the first signal line and a first power supply line because by providing different constant voltage signals, an uneven luminance phenomenon from happening to a display device can be prevented (see [0043] of Zhang).
Regarding claim 2, Kang further discloses the display substrate according to claim 1, wherein the pixel circuit further comprises a first reference transistor (Fig. 2A; [0118], e.g., T5), wherein a gate electrode of the first reference transistor is electrically connected with a fifth scan signal line (e.g., SL2i), a first electrode of the first reference transistor is electrically connected with a first reference signal line (e.g., VREF), and a second electrode of the first reference transistor is electrically connected with the second end of the first capacitor and the second end of the second capacitor (e.g., connected the second end N2 of C1 and the second end N2 of C2). Kang further discloses wherein the first reference signal line outputs an initializing voltage ([0069], [0141]-[0142], e.g., the third node N3 may be initialized to the voltage of the reference power source VREF).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the invention of Kang in view of Zhang for outputting a same signal to the first signal line and the first reference signal line so that the same initializing voltage can be used to initialize a second end of a second capacitor and a first end of the second capacitor.
Regarding claim 3, Kang further discloses the display substrate according to claim 1, further comprising: a light emitting structure layer disposed at a side of the drive circuit layer away from the base substrate (Fig. 7; [0254], [0278], e.g., the display element layer DPL disposed at a side of the pixel circuit layer PCL),
wherein the light emitting structure layer comprises at least a plurality of light emitting units (e.g., LD), at least one of the plurality of light emitting units comprises a cathode, and the cathode is connected with a second power supply line (Figs 2A and 7; e.g., the cathode CD is connected with a second power supply line VSS).
Zhang further discloses the pixel circuit wherein a light emitting unit comprises a cathode, and the cathode is connected with a second power supply line (Fig. 4; [0044]-[0045], [0049], .g., the cathode of the OLED is connected with a second power supply line VSS), and the first signal line and the second power supply line output a same signal ([0044], e.g., the voltage stabilizing signal terminal connected to C1 can be the second power supply line VSS).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the invention of Kang in view of Zhang for outputting a same signal to the first signal line and the second power supply line because a voltage level of the second power supply line can be used as a voltage stabilizing signal during driving process of a pixel circuit (see [0052] of Zhang).
Regarding claim 4, Kang further discloses the display substrate according to claim 1, wherein the first capacitor comprises at least a first electrode plate as the first end of the first capacitor and a third electrode plate as the second end of the first capacitor (Fig. 7; [0218], e.g., a first electrode plate C1_E1 and a third electrode plate C1_E2), wherein an orthographic projection of the first electrode plate on the base substrate is at least partially overlapped with an orthographic projection of the third electrode plate on the base substrate (e.g., the first electrode plate C1_E1 on the base substrate is at least partially overlapped with an orthographic projection of the third electrode plate C1_E2 on the base substrate);
the second capacitor comprises at least a second electrode plate as the second end of the second capacitor and a fourth electrode plate as the first end of the second capacitor ([0217], e.g., the second electrode plate C2_E1 and the fourth electrode plate VL_VDD),
wherein an orthographic projection of the second electrode plate on the base substrate is at least partially overlapped with an orthographic projection of the fourth electrode plate on the base substrate (e.g., an orthographic projection of the second electrode plate C2_E1 is partially overlapped with an orthographic projection of the fourth electrode plate VL_VDD on the base substrate);
the fourth electrode plate is connected with the first signal line (see Fig. 2A of Kang and Fig. 4 of Zhang, e.g., the fourth electrode VL_VDD is connected with the first signal line Vin)), the second electrode plate is connected with the third electrode plate, and the first electrode plate serves as the gate electrode of the drive transistor (Fig. 2A, e.g., the second electrode plate of C1 is connected with the third electrode plate of C2).
Regarding claim 8, Kang further discloses the display substrate according to claim 4, wherein
an orthographic projection of the first power supply connection line on the base substrate is partially overlapped with an orthographic projection of the first capacitor on the base substrate (Figs 6A and 7; e.g., orthographic projection of the first power supply connection line VDDL on the base substrate is overlapped with an orthographic projection of the first capacitor C1 on the base substrate).
Regarding claim 14, Kang further discloses the display substrate according to claim 4, wherein the drive circuit layer further comprises at least one first reference signal line extending along a first direction and at least one reference signal connection line extending along a second direction, the first direction and the second direction intersect (Figs 6A to 6F; [0246], e.g., the third power source line VREFL may extend in the second direction DR2 and may be connected to the (3_1)-th power source line VL_REF that is in the first direction DR1);
the first reference signal line is connected with the reference signal connection line to form a mesh structure for transmitting a first reference signal ([0248], e.g., the third power source line VREFL may extend in the second direction DR2, and the (3_1)-th power source line VL_REF connected to the third power source line VREFL through a contact hole may extend in the first direction DR1 and thus may have a mesh structure).
Zhang further discloses the pixel circuit wherein a first reference signal line serves a first signal line, and a fourth electrode plate of the second capacitor is connected with the first reference signal line (Fig. 3; [0044]-[0045], e.g., , the voltage stabilizing signal terminal may be the reference signal terminal Vref).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the invention of Kang in view of Zhang for using the first reference signal line serves as the first signal line so that an initializing signal can be outputted from the first reference signal line.
Regarding claim 16, Kang further discloses the display substrate according to claim l, wherein the pixel circuit further comprises a first initialization transistor (Fig. 2A, [0117], e.g., T4) and a compensation transistor ([0116], e.g., T3);
a gate electrode of the first initialization transistor is electrically connected with a first scan signal line (e.g., SL3i), a first electrode of the first initialization transistor is electrically connected with a first initial signal line (e.g., Vint), and a second electrode of the first initialization transistor is electrically connected with the gate electrode of the drive transistor (e.g., the gate electrode of T1);
a gate electrode of the compensation transistor is electrically connected with a second scan signal line (e.g., SL2i), a first electrode of the compensation transistor is electrically connected with the gate electrode of the drive transistor (e.g., the gate electrode of T1), and a second electrode of the compensation transistor is electrically connected with a second electrode of the drive transistor (e.g., the second electrode of T1).
Regarding claim 17, Kang further discloses the display substrate according to claim 16, wherein the at least one circuit unit further comprises a first shield electrode (Fig. 6A; [0220]), wherein an orthographic projection of the first shield electrode on the base substrate is at least partially overlapped with an orthographic projection of a first active layer between two gate electrodes of first initialization transistors in the circuit unit on the base substrate, and the orthographic projection of the first shield electrode on the base substrate is further at least partially overlapped with an orthographic projection of a second active layer between two gate electrodes of compensation transistors in an adjacent circuit unit on the base substrate ([0220], e.g., the third shielding pattern SHP3 may overlap the bent portion of the third and fourth sub-semiconductor regions ACT_T3 and ACT_T4).
Regarding claim 21, Kang further discloses the display substrate according to claim 16, wherein the pixel circuit further comprises a second light emitting control transistor (Fig. 2A; [0121], e.g., T7); a gate electrode of the second light emitting control transistor is electrically connected with a second light emitting signal line (e.g., EL2i), a first electrode of the second light emitting control transistor is electrically connected with the second electrode of the drive transistor (e.g., the second electrode of T1), and a second electrode of the second light emitting control transistor is electrically connected with a light emitting device (e.g., LD); the second light emitting signal line and the first light emitting signal line are of a same layer structure (FIGS. 6A to 6E, [0227]-[0228], e.g., the first emission control line EL1 and the second emission control line EL2 are of a same layer structure).
Regarding claim 22, Kang further discloses the display substrate according to claim l, wherein the pixel circuit (Fig. 2A) further comprises a second reference transistor (e.g., T9) and a second initialization transistor (e.g., T8);
a gate electrode of the second reference transistor is electrically connected with a fourth scan signal line (e.g., SL4i), a first electrode of the second reference transistor is electrically connected with a second reference signal line (e.g., Vbs), and a second electrode of the second reference transistor is electrically connected with the first electrode of the drive transistor (e.g., N5 of T1);
a gate electrode of the second initialization transistor is electrically connected with the fourth scan signal line (e.g., SL4i), a first electrode of the second initialization transistor is electrically connected with a second initial signal line (e.g., Vaint), and a second electrode of the second initialization transistor is electrically connected with a light emitting device (e.g., N4 of LD);
active layers of at least two adjacent second initialization transistors along a first direction are connected into an integral structure through a second active connection line (Fig. 6B; [0187], [0214]).
Regarding claim 23, Kang further discloses the display substrate according to claim 4, wherein in a direction perpendicular to the display substrate, the drive circuit layer comprises a semiconductor layer (Fig. 7; [0255], e.g., semiconductor layer ACT), a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially disposed on the base substrate ([0186], [0256], e.g., the semiconductor layer ACT, the first conductive layer GAT1, the second conductive layer GAT2, the third conductive layer SD1, and the fourth conductive layer SD2 are sequentially stacked on the base layer SUB),
active layers of the data writing transistor, the drive transistor, and the first light emitting control transistor are located in the semiconductor layer (Fig. 6B; e.g., active layers of T2, T1 and T6 are located in the semiconductor layer ACT);
gate electrodes of the data writing transistor, the drive transistor, and the first light emitting control transistor, the first electrode plate of the first capacitor, and the second electrode plate of the second capacitor are located in the first conductive layer (Figs 6A-6C; [0205]-[0206], e.g., the first conductive layer GAT1 may include an eleventh capacitor electrode C1_E1, a twenty-first capacitor electrode C2_E1, and gate patterns T2_GE, T3_GE, T4_GE, T5_GE, T6_GE, T7_GE, T8_GE, and T9_GE of the second to ninth transistors T2 to T9. The eleventh capacitor electrode C1_E1 may define the gate electrode of the first transistor T1);
the third electrode plate of the first capacitor and the fourth electrode plate of the second capacitor are located in the second conductive layer ([0216], e.g., the second conductive layer GAT2 may include a twelfth capacitor electrode C1_E2, the (1_1)-th power source line VL_VDD);
the third scan signal line is located in the third conductive layer ([0222]);
the first power supply line and the data signal line are located in the fourth conductive layer ([0243]).
Regarding claim 24, Kang further discloses a display apparatus, comprising the display substrate according to claim l (Fig. 1; [0065], e.g., display device 1000).
Regarding claim 25, Kang discloses a preparation method of a display substrate (Fig. 7; [0250], e.g., a display substrate 1000), comprising:
forming a drive circuit layer on a base substrate ([0254], e.g., forming a pixel circuit layer PCL on a base substrate SUB);
wherein the drive circuit layer comprises at least a plurality of circuit units, at least one of the plurality of circuit units comprises a pixel circuit (e.g., the pixel circuit layer PCL comprises a plurality of pixel circuits), and the pixel circuit at least a first capacitor (e.g., C1), a second capacitor (e.g., C2), a data writing transistor (e.g., T2), a drive transistor (e.g., T1), and a first light emitting control transistor (e.g., T6);
a first end of the first capacitor is electrically connected with a gate electrode of the drive transistor ([0113], e.g., a first end of C1 is connected with a gate electrode of T1), a second end of the first capacitor is electrically connected with a second end of the second capacitor (e.g., a second end of C1 is connected with a second end of C2), and a first end of the second capacitor is electrically connected with a first signal line (e.g., a first signal line VDD);
a gate electrode of the data writing transistor is electrically connected with a third scan signal line (e.g., a gate electrode of T2 is connected with a third scan signal line SL1i), a first electrode of the data writing transistor is electrically connected with a data signal line (e.g., data signal line DLj), and a second electrode of the data writing transistor is electrically connected with the second end of the first capacitor and the second end of the second capacitor (e.g., the second end of C1 and the second end of C2);
a gate electrode of the first light emitting control transistor is electrically connected with a first light emitting signal line (e.g., a gate electrode of T6 is connected with a first light emitting signal line EL1i), a first electrode of the first light emitting control transistor is electrically connected with a first power supply line (e.g., a first power supply line VDD), and a second electrode of the first light emitting control transistor is electrically connected with a first electrode of the drive transistor (e.g., a second electrode of T6 is connected with a first electrode of T1),
the first power supply line extends along a second direction (Figs 6A and 6F; [0248], e.g., first power supply line VL_VDD extends along a second direction DR1), and the drive circuit layer further comprises at least one first power supply connection line extending along a first direction ([0247]-[0248], e.g., first power supply connection line VDDL is extending along a first direction DR2), the first direction intersecting with the second direction (e.g., the first direction Dr1 intersects with the second direction DR2); the first power supply line is connected with the first power supply connection line to form a meshe structure for transmitting a first power supply signal ([0248], e.g., the power source line VL_VDD connected to the first power supply connection line VDDL through the third bridge pattern BRP3 and a contact hole may extend in the first direction DR1 and thus may have a mesh structure); and
the drive circuit layer further comprises at least one second power supply connection line extending along the first direction (Figs 6A-6F; [0243], e.g., at least one second power supply connection line VREFL extending along the first direction DR2) and at least one second power supply line extending along the second direction ([0246], e.g., at least one second power supply line VL_REF extending along the second direction DR1), the second power supply line is connected with the second power supply connection line to form a mesh structure for transmitting a second power supply signa ([0248], e.g., the second power supply line VL_REF is connected with the second power supply connection line VREFL to form a mesh structure for transmitting a second power supply signal VREF); and
the second power supply connection line is located at a side of the first power supply connection line close to the second capacitor (e.g., the second power supply connection line VREFL is located at a side of the first power supply connection line VDDL close to the second capacitor C2_E1).
Kang does not specifically disclose wherein the first signal line and the first power supply line are configured to provide different constant voltage signals.
However, Zhang discloses a pixel circuit (Fig. 4; [0045]) comprising: at least a first capacitor (e.g., C2), a second capacitor (e.g., C1), a data writing transistor (e.g., M4), a drive transistor (e.g., M3), and a first light emitting control transistor (e.g., M6),
wherein a first end of the second capacitor is electrically connected with a first signal line (e.g., Vin); a first electrode of the drive transistor is electrically connected with a first power supply line (e.g., VDD); and wherein the first signal line and the first power supply line are configured to provide different constant voltage signals ([0045], e.g., a voltage level of the initializing signal outputted from the initializing signal terminal Vin is always a first voltage level and a voltage level of the first power source signal outputted from the first power source signal terminal VDD is always a second voltage level).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the teachings of Zhang in the invention of Kang for electrically connecting a first end of the second capacitor is electrically connected with a first signal line and providing different constant voltage signals for the first signal line and a first power supply line because by providing different constant voltage signals, an uneven luminance phenomenon from happening to a display device can be prevented (see [0043] of Zhang).
Allowable Subject Matter
5. Claims 26-27 and 30 are allowed.
6. Claims 14-15 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for indicating allowable subject matter is that claim 26 recites “
the drive circuit layer further comprises at least one second power supply connection line extending along a first direction and at least one second power supply line extending along a second direction, the first direction intersecting with the second direction; the second power supply line is connected with the second power supply connection line to form a mesh structure for transmitting a second power supply signal; a portion of the second power supply connection line is located between the first capacitor and the second capacitor; the first signal line and the second power supply line transmit a same signal” which, in combination with the other features, are not taught and/or suggested either singularly or in combination within the prior art.
The primary reason for indicating allowable subject matter is that claim 14 recites “wherein the drive circuit layer further comprises at least one first reference signal line extending along a first direction and at least one reference signal connection line extending along a second direction, the first direction and the second direction intersect; the first reference signal line is connected with the reference signal connection line to form a mesh structure for transmitting a first reference signal; the first reference signal line serves as the first signal line, and the fourth electrode plate of the second capacitor is connected with the first reference signal line” which, in combination with the other features, are not taught and/or suggested either singularly or in combination within the prior art.
The primary reason for indicating allowable subject matter is that claim 19 recites “
wherein extension directions of the first initial signal line, the first scan signal line, and the second scan signal line are at least partially the same and the first initial signal line, the first scan signal line, and the second scan signal line are located at a same side of the first initialization transistor; the first initial signal line is located between the first scan signal line and the second scan signal line” which, in combination with the other features, are not taught and/or suggested either singularly or in combination within the prior art.
Conclusion
6. Any inquiry concerning this communication or earlier communications from the examiner should be directed to HONG ZHOU whose telephone number is (571)270-5372. The examiner can normally be reached 9:00-5:00 PM.
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/HONG ZHOU/Primary Examiner, Art Unit 2629
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