DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "a second crystal" in line 2. The limitation as written is unclear. The specification fails to disclose “a second crystal” and the claims fail to refer to the aforementioned “second crystal”. For examination purposes, examiner has interpreted “a second crystal” to read “a second transistor”.
By virtue of their dependency on claim 1, claims 2-9 are also rejected.
Claim 8 recites the limitation “the power divider” is line 4. There is insufficient antecedent basis for this limitation in the claim. For examination purposes, examiner has interpreted “the power divider” to read “a power divider”.
Claim 10 recites the limitation “of the second transistor and a second transistor” in line 3. There is insufficient antecedent basis for this limitation in the claim. For examination purposes, examiner has interpreted “of the second transistor and a second transistor” to read “ of a second transistor”.
By virtue of their dependency on claim 10, claims 11-20 are also rejected.
Claims 18-20 recites the limitation “the power threshold” in the second-to-last line of each claim. There is insufficient antecedent basis for this limitation in the claim. For examination purposes, examiner has interpreted “the power threshold” to read “a power threshold”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6, 8, & 10 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Maalouf et al. (US 2020/0358404 A1), hereinafter Maalouf.
Regarding claim 1, as best understood based on the 35 U.S.C. 112(b) rejection made above, Maalouf discloses, in figure 2, A method of controlling a power amplifier, the power amplifier comprising:
a first amplification path (24) comprising a first transistor (32) and a second transistor (34), an output port of the first transistor being electrically connected to a control port of the second transistor (output of transistor 32 is connected to the control port of transistor 34); and
a second amplification path (26) comprising a third transistor (38) and a fourth transistor (40), an output port of the third transistor being electrically connected to a control port of the fourth transistor (output of transistor 38 is connected to the control port of transistor 40), wherein the method comprises:
providing an input signal to the first amplification path and the second amplification path (RF IN provided to both amplification paths via the control ports of transistor 32 and transistor 38); and
supplying (Para [0041], “bias controller 28”) a first DC bias voltage and a second DC bias voltage to a control port of the third transistor and a control port of the fourth transistor respectively (bias controller 28 supplies first DC bias voltage Vgs3 to the control port of transistor 38 and a second DC bias voltage Vgs4 to the control port of the fourth transistor 40),
wherein current conduction trenches of the third transistor and the fourth transistor comprise same materials (Para [0036], “PA device 38, and a fourth PA device 40…is a transistor integrally formed on a semiconductor substrate (including silicon, gallium nitride, gallium arsenide, indium gallium phosphide, and/or other semiconductor substrates). For example, a “PA device” or a “reference device” may be a field effect transistor (FET) (e.g., a metal oxide semiconductor FET (MOSFET), a laterally diffused MOSFET (LDMOS FET), a high electron mobility transistor (HEMT), a heterojunction bipolar transistor (HBT), and so on)”…the third transistor 38 and fourth transistor 40 comprise same materials) and the first DC bias voltage is higher than the second DC bias voltage (Para [0051], “the third control voltage [Vgs3] is approximately 1.9 volts…the fourth control voltage [Vgs4] is approximately 1.8 volts”).
Regarding claim 2, Maalouf discloses the method according to claim 1, and continues to disclose, in figure 2, wherein each of the third transistor and the fourth transistor comprises a silicon transistor (Para [0036], “PA device 38, and a fourth PA device 40…is a transistor integrally formed on a semiconductor substrate (including silicon…”) and the difference between the first DC bias voltage and the second DC bias voltage is not higher than 0.5 volts (Para [0051], “the third control voltage [Vgs3] is approximately 1.9 volts…the fourth control voltage [Vgs4] is approximately 1.8 volts”…a difference of 0.1 volts).
Regarding claim 3, Maalouf discloses the method according to claim 2, and continues to disclose, in figure 2, wherein the difference between the first DC bias voltage and the second DC bias voltage is greater than or equal to 0.1 volts and less than or equal to 0.3 volts (Para [0051], “the third control voltage [Vgs3] is approximately 1.9 volts…the fourth control voltage [Vgs4] is approximately 1.8 volts”…a difference of 0.1 volts).
Regarding claim 4, Maalouf discloses the method according to claim 3, and continues to disclose, in figure 2, wherein the first DC bias voltage is greater than or equal to 1.9 volts and less than or equal to 2.2 volts (Para [0051], “the third control voltage [Vgs3] is approximately 1.9 volts”).
Regarding claim 5, Maalouf discloses the method according to claim 1, and continues to disclose, in figure 2, wherein each of the third transistor and the fourth transistor comprises a silicon transistor (Para [0036], “PA device 38, and a fourth PA device 40…is a transistor integrally formed on a semiconductor substrate (including silicon…”) and the second DC bias voltage is greater than 0 and less than or equal to 3 volts (Para [0051], “the fourth control voltage [Vgs4] is approximately 1.8 volts”).
Regarding claim 6, Maalouf discloses the method according to claim 5, and continues to disclose, in figure 2, wherein the second DC bias voltage is greater than or equal to 1.8 volts and less than or equal to 2.2 volts (Para [0051], “the fourth control voltage [Vgs4] is approximately 1.8 volts”).
Regarding claim 8, as best understood based on the 35 U.S.C. 112(b) rejection made above, Maalouf discloses the method according to claim 1, and continues to disclose, in figure 1 & 2, wherein the step of providing input signals to the first amplification path (24) and the second amplification path (26) comprises:
allocating the input signal to the first amplification path (Para [0040], “control terminal of the first PA device 32 is electrically coupled to RF IN (e.g., to output 18 of power splitter 6, FIG. 1)”) and the second amplification path using a power divider (Para [0042], “control terminal of the third PA device 38 is electrically coupled to RF IN (e.g., to output 16 of power splitter 6, FIG. 1)”).
Regarding claim 10, Maalouf discloses, in figure 2, a power amplifier, comprising:
a first amplification path (24) comprising a first transistor having an output port electrically connected to a control port of a second transistor (transistor 32 with output port electrically connected to a control port of a second transistor 34), the first amplification path being configured to obtain a first amplifying signal based on an input signal (Para [0040], “drain of the second PA device 34 is the node at which an RF output signal is output…with the RF output signal being an amplified version of the RF input signal”);
a second amplification path (26) comprising a third transistor (transistor 38) and a fourth transistor (transistor 40), the third transistor having an output port electrically connected to a control port of the fourth transistor (output port of transistor 38 connected to a control port of transistor 40), and a current conduction trench of the third transistor and the fourth transistor comprising same materials (Para [0036], “PA device 38, and a fourth PA device 40…is a transistor integrally formed on a semiconductor substrate (including silicon, gallium nitride, gallium arsenide, indium gallium phosphide, and/or other semiconductor substrates). For example, a “PA device” or a “reference device” may be a field effect transistor (FET) (e.g., a metal oxide semiconductor FET (MOSFET), a laterally diffused MOSFET (LDMOS FET), a high electron mobility transistor (HEMT), a heterojunction bipolar transistor (HBT), and so on)”…the third transistor 38 and fourth transistor 40 comprise same materials), the second amplification path being configured to obtain a second amplifying signal based on the input signal (Para [0042], “drain of the fourth PA device 40 is the node at which an RF output signal is output…with the RF output signal being an amplified version of the RF input signal”); and
a first power supply circuit configured to provide a first DC bias voltage and a second DC bias voltage to a control port of the third transistor and a control port of the fourth transistor respectively (Para [0045], “bias controller 28”…provides a first DC bias voltage Vgs3 to a control port of transistor 38 and a second DC bias voltage to a control port of the transistor 40), the first DC bias voltage being higher than the second DC bias voltage (Para [0051], “the third control voltage [Vgs3] is approximately 1.9 volts…the fourth control voltage [Vgs4] is approximately 1.8 volts”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7 & 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Maalouf.
Regarding claim 7, Maalouf discloses the method according to claim 1, and continues to disclose, in figure 2, wherein each of the first transistor, the third transistor, and the fourth transistor comprises a silicon transistor (Para [0036], “first power amplifier (PA) device 32…PA device 38, and a fourth PA device 40…is a transistor integrally formed on a semiconductor substrate (including silicon…”), but fails to disclose the second transistor comprising a gallium nitride transistor.
However, It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the gallium nitride material of the second transistor since Maalouf discloses the inclusion of the gallium nitride material (Para [0036], “PA device 34…integrally formed on a semiconductor substrate (including silicon, gallium nitride…”) and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art [i.e., utilizing differing materials that exhibit differing power handling capabilities for the transistors]. (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415‐421, 82 USPQ2d 1385).
Regarding claim 11, Maalouf discloses the power amplifier according to claim 10, and continues to disclose, in figure 2, wherein each of the first transistor, the third transistor, and the fourth transistor comprises a silicon transistor (Para [0036], “first power amplifier (PA) device 32…PA device 38, and a fourth PA device 40…is a transistor integrally formed on a semiconductor substrate (including silicon…”), but fails to disclose the second transistor comprising a gallium nitride transistor.
However, It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the gallium nitride material of the second transistor since Maalouf discloses the inclusion of the gallium nitride material (Para [0036], “PA device 34…integrally formed on a semiconductor substrate (including silicon, gallium nitride…”) and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art [i.e., utilizing differing materials that exhibit differing power handling capabilities for the transistors]. (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415‐421, 82 USPQ2d 1385).
Regarding claim 12, Maalouf discloses the power amplifier according to claim 11, and continues to disclose, in figure 4, wherein the power amplifier comprises a first sub-package structure comprising the second transistor and the fourth transistor (first sub-package structure mounting surface 312 comprises the second transistor and the fourth transistor mounted thereto).
Regarding claim 13, Maalouf discloses the power amplifier according to claim 12, and continues to disclose, in figure 4, wherein the first sub-package structure further comprises the first power supply circuit (bias controller 428 mounted on the first sub-package structure mounting surface 312).
Claims 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Maalouf as applied to claims 7 & 11-12 above, and further in view of Ohhashi et al. (US 11,942,911 B2), hereinafter Ohhashi.
Regarding claim 14, Maalouf discloses the power amplifier according to claim 12, but fails to disclose wherein the power amplifier further comprises a second sub-package structure comprising the first transistor and the third transistor, and the power amplifier further comprises a carrier board for carrying the first sub-package structure and the second sub-package structure.
However, Ohhashi discloses, in figure 7, wherein the power amplifier further comprises a second sub-package structure comprising the first transistor and the third transistor (monolithic semiconductor device 18 includes driver amplifier semiconductor device 15 that is a pre-amplifier for carrier amplifier semiconductor device 11 and includes semiconductor device 16 that is a pre-amplifier for peak amplifier semiconductor device 12…i.e., first transistors of respective amplifier paths are provided on the same sub-package structure 18), and the power amplifier further comprises a carrier board for carrying the first sub-package structure and the second sub-package structure (carrier board houses the semiconductor dies which carries sub-package structures 18, 19, 20, 13).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the second sub-package structure of Ohhasi in the carrier board of Maalouf, since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. [i.e., mounting transistors on dies as necessitated by design requirements] (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415‐421, 82 USPQ2d 1385).
Regarding claim 15, Maalouf discloses the power amplifier according to claim 11, and continues to disclose, in figure 4, wherein the power amplifier comprises a package structure and the package structure comprises:
a substrate (substrate 310); and
wherein the second transistor and the fourth transistor are attached to the substrate (second and fourth PA device transistor are attached to the substrate 310 via respective dies on the first sub-package structure mounting surface 312), but fails to disclose a third sub-package structure located on the substrate, the third sub-package structure comprising the first transistor and the third transistor.
However, Ohhashi discloses, in figure 7, a third sub-package structure located on the substrate (18 on substrate 100), the third sub-package structure comprising the first transistor and the third transistor (monolithic semiconductor device 18 includes driver amplifier semiconductor device 15 that is a pre-amplifier for carrier amplifier semiconductor device 11 and includes semiconductor device 16 that is a pre-amplifier for peak amplifier semiconductor device 12…i.e., first transistors of respective amplifier paths are provided on the same sub-package structure 18).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the second sub-package structure of Ohhasi in the carrier board of Maalouf, since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. [i.e., mounting transistors on dies as necessitated by design requirements] (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415‐421, 82 USPQ2d 1385).
Allowable Subject Matter
Claims 9 & 16-20 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Szymanowski et al. (US 2021/0194440 A1) [Figure 6. Discloses A multiple-stage amplifier includes a driver stage transistor characterized by a first power density, and a final stage transistor characterized by a second power density that is larger than the first power density. A first drain bias circuit is coupled to a first drain terminal of the driver stage transistor, and is configured to provide a first drain bias voltage to the first drain terminal. A second drain bias circuit is coupled to a second drain terminal of the final stage transistor, and is configured to provide a second drain bias voltage to the second drain terminal, where the second drain bias voltage equals the first drain bias voltage. An interstage impedance matching circuit is coupled between the first drain terminal and a gate terminal of the final stage transistor. The multiple-stage amplifier may be included in a Doherty power amplifier, a transceiver, and/or a transceiver array.]
Cui et al. (US 2014/0035678 A1) [Figure 6. Discloses a power amplifier apparatus and a power amplifier circuit. The power amplifier circuit uses a Doherty circuit structure, uses a High Electron Mobility Transistor (HEMT) power amplifier to implement a Carrier amplifier with the Doherty circuit structure, and uses a Laterally Diffused Metal Oxide Semiconductor Field Effect Transistor (LDMOS) to implement a Peak amplifier. With the power amplifier apparatus and power amplifier circuit of the present invention, the power amplifier efficiency is improved.]
Komatsuzaki et al. (US 12,658,856 B2) [Figure 1. Discloses a Doherty amplifier that includes a first filter circuit to output a first input signal obtained by attenuating an input signal lying in a first frequency band, and to output a second input signal obtained by allowing passage of an input signal lying in a second frequency band; a second filter circuit to output a third input signal obtained by attenuating an input signal lying in the first frequency band, and to output a fourth input signal obtained by attenuating an input signal lying in the second frequency band; a first amplifier to operate as an auxiliary amplifier when receiving the first input signal, and to operate as a main amplifier when receiving the second input signal; and a second amplifier tip operate as the main amplifier when receiving the third input signal, and to operate as the auxiliary amplifier when receiving the fourth input signal.]
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TYLER J PERENY whose telephone number is (571)272-4189. The examiner can normally be reached M-F 7:30-5.
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/TYLER J PERENY/ Examiner, Art Unit 2836
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