Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of the Information Disclosure Statement dated 07/10/2024.
The information disclosure statement filed 07/10/2024 in regard to “Making Information Transfer Efficient in Distributed Machine Learning Using Moving Image Compression Technology” fails to comply with the provisions of 37 CFR 1.97, 1.98 and MPEP § 609 because it has not been fully translated into English. It has been placed in the application file, but the information referred to therein has not been considered as to the merits. Applicant is advised that the date of any re-submission of any item of information contained in this information disclosure statement or the submission of any missing element(s) will be the date of submission for purposes of determining compliance with the requirements based on the time of filing the statement, including all certification requirements for statements under 37 CFR 1.97(e). See MPEP § 609.05(a).
All of the remaining cited references have been considered.
Drawings
The drawings have been received on 07/10/2024. These drawings are accepted.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier.
Such claim limitation(s) is/are:
“processing section” in claims 1, 8 and 9.
“transmission section” in claims 1, 4 and 9.
“bottleneck portion” in claims 1-11.
“compressor” in claims 4 and 5.
“edge processing device” in claim 7.
“intermediate processing device” in claim 7.
“receiving section” in claims 8 and 9.
“private transmission path” in claim 7.
“public transmission path” in claim 7.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 2, 3, 7, 8, 9 and 10 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “minimum” in claims 1, 2, 3, 7, 8, 9 and 10 is a relative term which renders the claim indefinite. The term “minimum” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. For purposes of examination, Examiner is interpreting “minimum” as data transmitted is less than the portion right before and after the bottleneck.
The term “extremely small” in claims 1, 2, 3, 7, 8, 9 and 10 is a relative term which renders the claim indefinite. The term “extremely small” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. For purposes of examination, Examiner is interpreting “extremely small” as data transmitted is less than the portion right before and after the bottleneck.
Dependent claims 4-6 and 11-13 do not resolve the issue and are rejected with the same rationale.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 9 is rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claims do not fall within at least one of the four categories of patent eligible subject matter because the claims recite "computer-readable recording medium". The specification does not define the " computer-readable recording medium" to exclude "signals per se"; therefore, the broadest reasonable interpretation of " computer-readable recording medium" includes signals per se and not statutory.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 4, 5, 6, 8 and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Matsubara et al. (Split Computing and Early Exiting for Deep Learning Applications: Survey and Research Challenges); hereinafter Matsubara
Regarding claim 1, Matsubara teaches an information processing apparatus comprising: a processing section that processes data using a first neural network which constitutes a part of an overall neural network and (Matsubara [page 5, 2.2 Split Computing and Early Exiting]: “We consider a neural model M(·) with 𝐿 layers, and define zℓ the output of the ℓ-th layer. Early implementations of SC select a layer ℓ and divide the model M(·) to define the head and tail submodels”; Note: The head submodel is the first neural network.)
includes, in an output portion, a bottleneck portion where the amount of transmission data is minimum or extremely small in the overall neural network; and (Matsubara [page 10]: “concatenation of M𝐷 and M𝑇 is the tail model. Then, the tensor z is transmitted over the channel. The objective of the architecture is to minimize the size of z to reduce the communication time while also minimizing the complexity of M𝐸 (that is, the part of the model executed at the– weaker– mobile device) and the discrepancy between y and
y
^
. The layer between M𝐸 and M𝐷 is the injected bottleneck.”)
a transmission section that transmits data of the bottleneck portion of the first neural network, obtained by the processing using the first neural network performed by the processing section, to the outside. (Matsubara [page 10]: “concatenation of M𝐷 and M𝑇 is the tail model. Then, the tensor z is transmitted over the channel. The objective of the architecture is to minimize the size of z to reduce the communication time while also minimizing the complexity of M𝐸 (that is, the part of the model executed at the– weaker– mobile device) and the discrepancy between y and
y
^
. The layer between M𝐸 and M𝐷 is the injected bottleneck.”)
Regarding claim 2, Matsubara teaches the bottleneck portion is a portion where the amount of transmission data in the overall neural network in a portion not bypassed by a shortcut connection is minimum or extremely small. (Matsubara [page 9, 4.2. The Need for Bottleneck Injection]: “Without such natural bottlenecks in the model, naive splitting approaches would fail to improve performance in most settings [6, 33]. Some models, such as AlexNet [62], VGG [120] and DenseNet [49], possess such layers [87].”; Note: AlexNet and VGC do not have shortcut connections.)
Regarding claim 4, Matsubara teaches a compressor that compresses the data of the bottleneck portion, (Matsubara [page 5, 2.2 Split Computing and Early Exiting]: “a bottleneck is a compression point at one layer in the model, which can be realized by reducing the number of nodes of the target layer, and/or by quantizing its output.”; Note: Reducing the number of nodes is reducing the channel count.)
wherein the transmission section transmits data compressed by the compressor. (Matsubara [page 5, 2.2 Split Computing and Early Exiting]: “We consider a neural model M(·) with 𝐿 layers, and define zℓ the output of the ℓ-th layer. Early implementations of SC select a layer ℓ and divide the model M(·) to define the head and tail submodels”; Note: zℓ is the feature map.)
Regarding claim 5, Matsubara teaches the data of the bottleneck portion includes a feature map, and (Matsubara [page 5, 2.2 Split Computing and Early Exiting]: “We consider a neural model M(·) with 𝐿 layers, and define zℓ the output of the ℓ-th layer. Early implementations of SC select a layer ℓ and divide the model M(·) to define the head and tail submodels”; Note: zℓ is the feature map.)
the compression by the compressor includes at least one of
data compression by quantization, and (Matsubara [page 11]: “Their student model (namely, Entropic Student) contains a lightweight encoder with a learnable prior, which quantizes and entropy-codes latent representations under a prior prob ability model for efficiently saving the size of data to be offloaded to edge server.”)
data compression by entropy coding. (Matsubara [page 11]: “Their student model (namely, Entropic Student) contains a lightweight encoder with a learnable prior, which quantizes and entropy-codes latent representations under a prior prob ability model for efficiently saving the size of data to be offloaded to edge server.”)
Regarding claim 6, Matsubara teaches an information processing system comprising: a first information processing apparatus that is the information processing apparatus according to claim 1; and (Matsubara [page 5, 2.2 Split Computing and Early Exiting]: “We consider a neural model M(·) with 𝐿 layers, and define zℓ the output of the ℓ-th layer. Early implementations of SC select a layer ℓ and divide the model M(·) to define the head and tail submodels”; and [page 3]: “Split computing and early exit approaches are contextualized in a setting where the system is composed of a mobile device and an edge server interconnected via a wireless channel.”; Note: The head submodel is the first neural network.)
a second information processing apparatus that processes data of the bottleneck portion of the first neural network of the first information processing apparatus using a second neural network constituting the remainder of the overall neural network. (Matsubara [page 10]: “concatenation of M𝐷 and M𝑇 is the tail model. Then, the tensor z is transmitted over the channel. The objective of the architecture is to minimize the size of z to reduce the communication time while also minimizing the complexity of M𝐸 (that is, the part of the model executed at the– weaker– mobile device) and the discrepancy between y and
y
^
. The layer between M𝐸 and M𝐷 is the injected bottleneck.”)
Regarding claim 8, Matsubara teaches an information processing apparatus comprising: a receiving section that receives, from the outside, data of a bottleneck portion of a first neural network which constitutes a part of an overall neural network and includes the bottleneck portion in an output portion, the bottleneck portion being a portion where the amount of transmission data is minimum or extremely small in the overall neural network; and (Matsubara [page 5, 2.2 Split Computing and Early Exiting]: “We consider a neural model M(·) with 𝐿 layers, and define zℓ the output of the ℓ-th layer. Early implementations of SC select a layer ℓ and divide the model M(·) to define the head and tail submodels”; Note: The head submodel is the first neural network.)
a processing section that processes the data of the bottleneck portion of the first neural network received by the receiving section using a second neural network constituting the remainder of the overall neural network. (Matsubara [page 10]: “concatenation of M𝐷 and M𝑇 is the tail model. Then, the tensor z is transmitted over the channel. The objective of the architecture is to minimize the size of z to reduce the communication time while also minimizing the complexity of M𝐸 (that is, the part of the model executed at the– weaker– mobile device) and the discrepancy between y and
y
^
. The layer between M𝐸 and M𝐷 is the injected bottleneck.”)
Regarding claim 9, Matsubara teaches a computer-readable recording medium that records a program for causing a computer to function as: a processing section that processes data using a first neural network which constitutes a part of an overall neural network and includes, in an output portion, a bottleneck portion where the amount of transmission data is minimum or extremely small in the overall neural network; and (Matsubara [page 10]: “concatenation of M𝐷 and M𝑇 is the tail model. Then, the tensor z is transmitted over the channel. The objective of the architecture is to minimize the size of z to reduce the communication time while also minimizing the complexity of M𝐸 (that is, the part of the model executed at the– weaker– mobile device) and the discrepancy between y and
y
^
. The layer between M𝐸 and M𝐷 is the injected bottleneck.”)
a processing section that processes the data of the bottleneck portion of the first neural network received by the receiving section using a second neural network constituting the remainder of the overall neural network. (Matsubara [page 5, 2.2 Split Computing and Early Exiting]: “We consider a neural model M(·) with 𝐿 layers, and define zℓ the output of the ℓ-th layer. Early implementations of SC select a layer ℓ and divide the model M(·) to define the head and tail submodels”; Note: The head submodel is the first neural network.)
a transmission section that transmits data of the bottleneck portion of the first neural network, obtained by the processing performed by the processing section, to the outside. (Matsubara [page 10]: “concatenation of M𝐷 and M𝑇 is the tail model. Then, the tensor z is transmitted over the channel. The objective of the architecture is to minimize the size of z to reduce the communication time while also minimizing the complexity of M𝐸 (that is, the part of the model executed at the– weaker– mobile device) and the discrepancy between y and
y
^
. The layer between M𝐸 and M𝐷 is the injected bottleneck.”)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Matsubara et al. (Split Computing and Early Exiting for Deep Learning Applications: Survey and Research Challenges); hereinafter Matsubara in view of Eshratifar et al. (BottleNet: A Deep Learning Architecture for Intelligent Mobile Cloud Computing Services); hereinafter Eshratifar
Claim 3 is rejected over Matsubara and Eshratifar with incorporation of claim 1.
Regarding claim 3, Matsubara teaches wherein the bottleneck portion is at least one of a portion where the number of channels is minimum or extremely small in the overall neural network, and (Matsubara [page 5, 2.2 Split Computing and Early Exiting]: “a bottleneck is a compression point at one layer in the model, which can be realized by reducing the number of nodes of the target layer, and/or by quantizing its output.”; Note: Reducing the number of nodes is reducing the channel count.)
Matsubara does not appear to explicitly teach a portion where a cell size of a feature map is minimum or extremely small in the overall neural network.
However, Eshratifar teaches a portion where a cell size of a feature map is minimum or extremely small in the overall neural network. (Eshratifar [page 3]: “Spatial reduction unit takes a tensor of size (batch_size,w,h,c) as input, and outputs a tensor of size (batch_size,w′,h′,c) by applying a convolution filter of size (wf , hf, c, c) followed by normalization and non-linearity layers. The output tensor of the reduction unit is the reduced-order representation of its input (w′ < w, and h′ < h).”)
It would have been obvious before the effective filing date to combine bottleneck compression of Matsubara with the BottleNet deep learning architecture of Eshratifar to compensate for potential accuracy loss due to compression (Eshratifar, Abstract). Matsubara and Eshratifar are analogous art because they both concern using a bottleneck architecture in regards to data compression.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Matsubara in view of Gomez et al. (US 20160098646 A1); hereinafter Gomez
Claim 7 is rejected over Matsubara and Gomez with incorporation of claim 1.
Regarding claim 7, Matsubara teaches the first information processing apparatus includes:
an edge processing device that processes data using a neural network which constitutes a part of the first neural network and includes, in an output portion, a bottleneck portion where the amount of transmission data is minimum or extremely small in the first neural network; and (Matsubara [page 5, 2.2 Split Computing and Early Exiting]: “We consider a neural model M(·) with 𝐿 layers, and define zℓ the output of the ℓ-th layer. Early implementations of SC select a layer ℓ and divide the model M(·) to define the head and tail submodels”; and [page 10]: “concatenation of M𝐷 and M𝑇 is the tail model. Then, the tensor z is transmitted over the channel. The objective of the architecture is to minimize the size of z to reduce the communication time while also minimizing the complexity of M𝐸 (that is, the part of the model executed at the– weaker– mobile device) and the discrepancy between y and
y
^
. The layer between M𝐸 and M𝐷 is the injected bottleneck.”; Note: The head submodel is the first neural network.)
an intermediate processing device that processes data of the bottleneck portion of the neural network of the edge processing device using a neural network which constitutes the remainder of the first neural network and includes, in an output portion, the bottleneck portion where the amount of transmission data is minimum or extremely small in the overall neural network, (Matsubara [page 10]: “concatenation of M𝐷 and M𝑇 is the tail model. Then, the tensor z is transmitted over the channel. The objective of the architecture is to minimize the size of z to reduce the communication time while also minimizing the complexity of M𝐸 (that is, the part of the model executed at the– weaker– mobile device) and the discrepancy between y and
y
^
. The layer between M𝐸 and M𝐷 is the injected bottleneck.”)
the second information processing apparatus processes data of the bottleneck portion of the neural network of the intermediate processing device, (Matsubara [page 16]: “the intermediate output is forwarded to the edge server, where inference will continue using a mid-sized neural model with another exit. If the output still does not reach the target confidence, the intermediate layer’s output is forwarded to the cloud, which executes the largest neural model.”)
Matsubara does not appear to explicitly teach data is transmitted from the edge processing device to the intermediate processing device via a private transmission path, and
data is transmitted from the intermediate processing device to the second information processing apparatus via a public transmission path.
However, Gomez teaches data is transmitted from the edge processing device to the intermediate processing device via a private transmission path, and (Gomez [0046]: “ the user device 602 may include a wearable device and the connection 608 may include a proximity data network (e.g., Bluetooth).”)
data is transmitted from the intermediate processing device to the second information processing apparatus via a public transmission path. (Gomez [0046]: “User devices 602, 603 are coupled via data connection 608 and user device 603 is coupled to server device 604 via data connection 610.”)
It would have been obvious before the effective filing date to combine bottleneck compression of Matsubara with the user device and a server of Gomez to improve performance (Gomez, [0026]). Matsubara and Gomez are analogous art because they both concern split neural network architecture for data transmission.
Claims 10 and 11 rejected under 35 U.S.C. 103 as being unpatentable over Matsubara in view of Pei et al. (US 20210042889 A1); hereinafter Pei
Claim 10 is rejected over Matsubara and Pei.
Regarding claim 10, Matsubara teaches bottleneck portion where the amount of transmission data is minimum or extremely small in the overall neural network; and (Matsubara [page 10]: “concatenation of M𝐷 and M𝑇 is the tail model. Then, the tensor z is transmitted over the channel. The objective of the architecture is to minimize the size of z to reduce the communication time while also minimizing the complexity of M𝐸 (that is, the part of the model executed at the– weaker– mobile device) and the discrepancy between y and
y
^
. The layer between M𝐸 and M𝐷 is the injected bottleneck.”)
Matsubara does not appear to explicitly teach by a second information processing apparatus, preparing, according to a capability of a first information processing apparatus, a first neural network that constitutes a part of an overall neural network and includes, in an output portion, [a bottleneck portion where the amount of transmission data is minimum or extremely small in the overall neural network; and]
by the second information processing apparatus, transmitting the prepared first neural network to the first information processing apparatus.
However, Pei teaches by a second information processing apparatus, preparing, according to a capability of a first information processing apparatus, a first neural network that constitutes a part of an overall neural network and includes, in an output portion, [a bottleneck portion where the amount of transmission data is minimum or extremely small in the overall neural network; and] (Pei [0041]: “Operation 2: Train, based on a high-accuracy large model, a small model having a low recognition accuracy and a small computing workload by using a neural network compression technology (e.g., a model compression technology) to finally match a computing capability of an embedded device (e.g., a mobile device).”)
by the second information processing apparatus, transmitting the prepared first neural network to the first information processing apparatus. (Pei [0057]: “the mobile device receives the first sub-model transmitted by a second server,”)
It would have been obvious before the effective filing date to combine bottleneck compression of Matsubara with the sub-model compression of Pei to reduce computational workload (Pei, [0126]). Matsubara and Pei are analogous art because they both concern data compression.
Claim 11 is rejected over Matsubara and Pei with incorporation of claim 10.
Regarding claim 11, Matsubara teaches by the first information processing apparatus, processing data using the first neural network and transmitting data of the bottleneck portion of the first neural network obtained by the processing to the second information processing apparatus; and (Matsubara [page 10]: “concatenation of M𝐷 and M𝑇 is the tail model. Then, the tensor z is transmitted over the channel. The objective of the architecture is to minimize the size of z to reduce the communication time while also minimizing the complexity of M𝐸 (that is, the part of the model executed at the– weaker– mobile device) and the discrepancy between y and
y
^
. The layer between M𝐸 and M𝐷 is the injected bottleneck.”)
by the second information processing apparatus, processing the data of the bottleneck portion of the first neural network of the first information processing apparatus using a second neural network constituting the remainder of the overall neural network. (Matsubara [page 5, 2.2 Split Computing and Early Exiting]: “We consider a neural model M(·) with 𝐿 layers, and define zℓ the output of the ℓ-th layer. Early implementations of SC select a layer ℓ and divide the model M(·) to define the head and tail submodels”; and [page 10]: “concatenation of M𝐷 and M𝑇 is the tail model. Then, the tensor z is transmitted over the channel. The objective of the architecture is to minimize the size of z to reduce the communication time while also minimizing the complexity of M𝐸 (that is, the part of the model executed at the– weaker– mobile device) and the discrepancy between y and
y
^
. The layer between M𝐸 and M𝐷 is the injected bottleneck.”; Note: The head submodel is the first neural network.)
Claims 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Matsubara and Pei in view of Cricri et al. (WO 2019162568 A1); hereinafter Cricri
Claim 12 is rejected over Matsubara, Pei and Cricri with incorporation of claim 10.
Regarding claim 12, Matsubara does not appear to explicitly teach by the first information processing apparatus, changing a range of the first neural network in the overall neural network according to a situation of the first information processing apparatus; and
by the second information processing apparatus, changing a range of the second neural network in the overall neural network according to the situation of the first information processing apparatus.
However, Cricri teaches by the first information processing apparatus, changing a range of the first neural network in the overall neural network according to a situation of the first information processing apparatus; and (Cricri [lines 5-17]: “9.1 may comprise providing capability data from the first device 23. Capability data may be indicative of the first device’s capability to implement the assigned layer or combination of layers, as signalled, or it may be provided before initialisation of the neural network. For example, the provided capability data may be indicative of one or both of a device’s computational capability and memory capability. Alternatively, or additionally, the received capability data may be indicative of one or more of the device’s batteiy status,”; and [lines 19-24]: “9.2 may comprise transmitting the capability data to the neural 20 network control apparatus 22.”)
by the second information processing apparatus, changing a range of the second neural network in the overall neural network according to the situation of the first information processing apparatus. (Cricri [lines 25-30]: “this case, one or more of said device's layers may be duplicated in another device, as backup should the battery expire.”)
It would have been obvious before the effective filing date to combine bottleneck compression of Matsubara with the capability data containing battery status of Cricri to efficiency assign neural network architectures to different devices based on device capabilities (Cricri, pages 31-32, lines 35-4). Cricri and Matsubara are analogous art because they both concern dynamic partitioning of neural network layers.
Claim 13 is rejected over Matsubara, Pei and Cricri with incorporation of claim 10.
Regarding claim 13, Matsubara does not appear to explicitly teach the situation of the first information processing apparatus includes at least one of a situation of generation of heat and
a situation of the amount of remaining battery.
However, Cricri teaches the situation of the first information processing apparatus includes at least one of
a situation of the amount of remaining battery. (Cricri [lines 20-25]: “The transmitted capability data may be indicative of one or more of the device’s battery status, expected computational workload, expected memory workload, maximum processor speed, average memory consumption, maximum processor load and average processor load.”
It would have been obvious before the effective filing date to combine bottleneck compression of Matsubara with the capability data containing battery status of Cricri to efficiency assign neural network architectures to different devices based on device capabilities (Cricri, pages 31-32, lines 35-4). Cricri and Matsubara are analogous art because they both concern dynamic partitioning of neural network layers.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID H TRAN whose telephone number is (703)756-1525. The examiner can normally be reached M-F 9:30 am - 5:30 pm.
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/DAVID H TRAN/Examiner, Art Unit 2147
/ERIC NILSSON/Primary Examiner, Art Unit 2151
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