DETAILED ACTION
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11 July 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
The information disclosure statement (IDS) submitted on 20 November 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-5, and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Julien (US 20220417323 A1) “Julien ‘323” in view of Che (US 20170353397 A1) in further view of KYOUNGSOO (KR102479757B1) and in further view of Julien (US 20240419513 A1) “Julien ‘513”.
As for Claims 1, 5, and 6, Julien ‘323 discloses An arithmetic processing offload system (fig. 15A; [0138]) comprising a client (i.e., client application 102 that exists on host 3041 – Fig.3) and a server (server application 108 that exists on host 3042 – fig.3) connected thereto via a network (i.e. Network infrastructure 106 – Fig.3 ) and a network interface card (NIC)(i.e. Smart-NIC 3021 and 3022 – Fig.3).
Julien ‘323 does not disclose, the client configured to offload specific processing of an application to an accelerator installed in the server in order to perform arithmetic processing.
In an analogous art, Che discloses the client configured to offload specific processing of an application to an accelerator installed in the server in order to perform arithmetic processing (i.e. a client sending GPU computation kernel code and data to a server having GPU compute resources so that the server GPU (i.e. accelerator) executes the offloaded application processing (e.g. a client sends the server GPU computation kernel code and associated data for the GPU where the GPU executes the kernel to perform arithmetic operations on the data. The data is then sent back to the client) (¶0021-0024, 0019, 0016-0018)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Julien ‘323 to include the client configured to offload specific processing of an application to an accelerator installed in the server in order to perform arithmetic processing, as taught by Che, for the benefit of increasing computational efficiency and reducing the processing burden on the server processor by allowing arithmetic intensive application processing to be executed by the GPU accelerator, thereby enabling faster execution of the offloaded application processing and more efficient use of server compute resources.
Julien ‘323 fails to disclose wherein the server includes a userland application configured to cooperate with the accelerator while bypassing an OS.
In an analogous art, Kyoungsoo discloses wherein the server includes a userland application configured to cooperate with the accelerator while bypassing an OS ( i.e. a TCP application (userland application) uses offload API functions such as offload_open() and offload_write() to offload file/network I/O data plane operations to a SmartNIC/ NIC stack, where the SmartNIC performs content fetching, buffer management, packet generation, and transmission, thereby reducing the conventional OS/CPU/main-memory I/O path.)(¶0076, 0083, 0162)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Julien ‘323 to include wherein the server includes a userland application configured to cooperate with the accelerator while bypassing an OS, as taught by Kyoungsoo for the benefit of, reducing operating system latency by allowing the userland application to directly communicate with the accelerator/NIC data path.
Julien ‘323 fails to disclose and wherein the userland application includes an accelerator (ACC)-NIC common data parsing part configured to parse reception data in which an input data format of an ACC utilizing function and an NIC reception data format are made common.
In an analogous art, Julien ‘513 discloses and wherein the userland application includes an accelerator (ACC)-NIC common data parsing part (i.e. The hardware accelerated application kernel and data extraction function 601, also referred to herein as the kernel extraction function, extracts the kernels in a hardware accelerated application along with their dependencies) (¶0084)
configured to parse reception data in which an input data format of an ACC utilizing function(i.e. However, The required kernel input data can be extracted directly from the original application itself, e.g., when the input data would be provided as static input to the application. The kernel input data repository can include multiple generic common data types already available and compatible with the required kernel input data type, in order to characterize the kernel. [0088] FIG. 7 is a flowchart of one embodiment of the kernel extraction procedure. The kernel extraction procedure analyzes (e.g., parses) the hardware accelerated application (Block 701) and finds the locations of the definitions of kernels (Block 703). For every kernel (Block 705), the process parses the kernel code and identifies the dependencies such as the accessed non-local variables, called functions, and user-defined data types (e.g., user-defined classes) (Block 707). (¶ 0087 and 0088)(Block 701,703,705,707 – Fig.7 )
and an NIC reception data format (i.e. computing nodes can provide CPU’s, accelerators such as GPU’s, smart NICs, and FPGAs. That puts NICS and accelerators in the same environment which means generic common data would be sent to the NIC. )(¶0064) are made common (i.e. the kernel input data can include multiple generic common data types already available and compatible with the required kernel input data type)(¶0087)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Julien ‘323 to include wherein the userland application includes an accelerator (ACC)-NIC common data parsing part configured to parse reception data in which an input data format of an ACC utilizing function and an NIC reception data format are made common, as taught in Julien ‘513, for the benefit of reducing the need for separate format-conversion between the NIC reception data and the accelerator input data, thereby enabling the userland application to more efficiently prepare and route received data for accelerator processing.
As for Claim 4, Julien ‘323, Che, Kyoungsoo, and Julien ‘513 disclose, in particular Kyoungsoo discloses The arithmetic processing offload system according to claim 1, further comprising an ACC offload successive instruction part (i.e. IO-TCP host stack command logic that handles offloaded send commands and causes the NIC stack to successively perform packet processing)(¶0076-0077, 0083) configured to perform data arrival check on the NIC by polling in a busy loop(i.e. The NIC stack is implemented in a DPDK application (¶0108). DPDK applications inherently rely on poll-mode driver processing to poll NIC receive/transmit descriptors rather than relying on interrupt driven kernel stack processing.), and when data has arrived, perform reception processing (i.e. the host stack and nic stack split where the NIC stack receives custom commands such as OPEN,CLOS,SEND and ACKD, and processes the offloaded data operations.)(¶0031-0032, 0034, 0104, 0178)and instruct the ACC-NIC common data parsing part to, in succession to the processing, successively perform parsing of ACC offload processing.(i.e. when the NIC stack receives a SEND command, it reads file contents, generates TSO/TCP packets using the command packets TCP/IP header and sends them to the NIC hardware data plane for partitioning and checksum calculations. )(¶0083)
Motivation to combine is similar to that of Claim 1.
Claims 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Julien ‘323 in view of Che, Kyoungsoo, and Julien ‘513 and in further view of Kutch (US 20210117360 A1).
As for Claim 2, Julien ‘323, Che, Kyoungsoo, and Julien ‘513 fail to disclose The arithmetic processing offload system according to claim 1, further comprising a distributed data ACC collective transfer instruction part configured to instruct the accelerator to collectively transfer data received in a distributed manner as packets by the ACC-NIC common data parsing part as is to the accelerator in a state of being distributed on a memory of a userland.
In an analogous art, Kutch discloses a distributed data ACC collective transfer instruction part(i.e. SGL descriptors collectively expose distributed packet buffers to the accelerator. This allows the same functionality as the acc collective transfer instruction part by allowing the data to exist in separate places instead of concatenating the data together into one larger buffer.)(¶ 0349) configured to instruct the accelerator to collectively transfer data received in a distributed manner as packets by the ACC- NIC common data parsing part as is to the accelerator in a state of being distributed on a memory of a userland.(i.e. software is used to bind NIC queue pairs and use descriptors/ scatter-gather lists for NIC-received packets, thereby allowing packet data distributed in memory buffers to be collectively made accessible/transferred to the offload processing device instead of being sent from one larger memory location.)(¶ 0349 -0350, 0354, and 0356-0357)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Julien ‘323 in view of Che, Kyoungsoo, and Julien ‘513 to include The arithmetic processing offload system according to claim 1, further comprising a distributed data ACC collective transfer instruction part configured to instruct the accelerator to collectively transfer data received in a distributed manner as packets by the ACC-NIC common data parsing part as is to the accelerator in a state of being distributed on a memory of a userland as taught by Kutch for the benefit of allowing the offload processing device (accelerator) to access and process data mainained in distributed buffer locations without firest requiring the userland application or host CPU to concatenate the packet data into a single contiguous block, thereby conserving host processing resources.
As for Claim 3, Julien ‘323, Che, Kyoungsoo, and Julien ‘513 fail to disclose The arithmetic processing offload system according to The arithmetic processing offload system according to wherein the distributed data ACC collective transfer instruction part is further configured to, based on an inputted list of a plurality of unconcatenated data areas, instruct a distributed data transfer function of the accelerator to collectively transfer data of a plurality of areas to the accelerator without performing data concatenation.
In an analogous art, Kutch discloses wherein the distributed data ACC collective transfer instruction part (i.e. SGL mechanism plus software queue pair binding the tells/enables the offload processing device (accelerator) to access the listed buffers.)(¶0354) is further configured to, based on an inputted list of a plurality of unconcatenated data areas(i.e. the scatter gather list identifies separate packet buffer areas)(¶0179), instruct a distributed data transfer function of the accelerator to collectively transfer data of a plurality of areas to the accelerator (i.e. makes packets arriving at the nic accessible to offload processing device(accelerator) through bound queue pairs.)(¶0354) without performing data concatenation (i.e. because the SGL identifies multiple separate buffers, the offload device can access them without first copying them into one contiguous buffer.)(¶0179-0180)
Motivation to combine is similar to that of Claim 2.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Publication No. 2017/0180273 to Daly teaches that DPDK applications inherently use poll-based processing.
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/J.E./Examiner, Art Unit 2451
/Chris Parry/Supervisory Patent Examiner, Art Unit 2451
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