DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after allowance or after an Office action under Ex Parte Quayle, 25 USPQ 74, 453 O.G. 213 (Comm'r Pat. 1935). Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant's submission filed on 07-30-26 has been entered.
Claim 8 was previously canceled.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3-7 and 13 is/are rejected under 35 U.S.C. 102as being anticipated by
AAPA, NPL to Afoakwa et al., (CMOS Ising Machines with Coupled Bistable Nodes, arXiv:2007.06665v1 [quant-ph] 13 Jul 2020) of record.
Re claims 1:
The AAPA, NPL to Afoakwa et al, see highlighted figure 8 below, shows
a computation node, with an input(IN+) an output(out+);
a bistable node(ZIV structure), comprising an input(by M2,M4) and an output( by M1,M3), the output configured to have at least two equilibrium output voltages; These output voltages(-/+ 2.3 v) are output from the ZIV structure in this embodiment(for figure 8).
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a first buffer circuit(M17,M18), having an input and an output, the buffer input(M18 gate) connected to the output of the bistable node and the buffer output(M17 gate) connected to the output(out+) of the computation node, the buffer circuit configured to provide a first output voltage when a voltage at the buffer input is below a threshold, and a second output voltage when the voltage at the buffer input is above the threshold(i.e. buffer transistors on/off); and
a current conveyor(CCCS M22-M26) node having an input(between M22,M24) connected to the input of the computation node(IN+) and an output(M23,M25) connected to the input(M2 side) of the bistable node, the current conveyor configured to hold its input at a constant voltage and mirror(M25,M26) current received at the input into the input of the bistable node.
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Re claims 1 and 4:
As noted in the reference, p. 754, top left column, ll 6-9:…”the spin of the node can be read out by a digital latch (e.g., a D flip-flop) connected to the ZIV diode’s V + terminal. This converts the spin to a bit (1 or 0).”, that is, at the first buffer output+, the logic gate, such as a D latch/ flip-flop is considered. Inherently, this goes for the other buffer output- for the spin to be read out there.
Re claim 3: The computation node of claim 1, the computation node further comprising:
a second, inverting output(OUT-); and
a second buffer circuit(M6,7) having an input(M6 gate) connected to an inverting output of the bistable(ZIV) node, the inverting output of the bistable node configured to have an inverse value(OUT-) of the output of the bistable node(OUT+), the second buffer circuit further comprising an output(M7 gate) connected to the second inverting output of the computation node.
Re claim 5:
a second, inverting input(IN-); and
a second current conveyor(M11,12,14,15) node having an input (between m12,13)connected to the second inverting input(IN-) of the computation node and an output connected to a second input of the bistable node(above M4), the current conveyor configured to hold its input at a constant voltage and mirror current received at the input into the second input of the bistable node.
Re claims 6 and 7, see figure 2 embodiment, for a computation node representation with
resistive coupling nodes with inputs from other computation nodes being coupled in, forming the network.
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Re claim 13: a D Latch is a regenerative type latch with feedback.
Allowable Subject Matter
Claims 9-12 and 15 are allowed.
Claim 2 and 14 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARNOLD M KINKEAD whose telephone number is (571)272-1763. The examiner can normally be reached M-F 7am-5:30pm(Fri-Flex).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at 571-270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ARNOLD M KINKEAD/ Primary Examiner, Art Unit 2836
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