DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 33-38 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Korean Patent No. 10-2007-0061978 Kim et al.
1. Referring to claim 33, Kim et al. teaches an array substrate, comprising: a base substrate, (Figures 4-5 #100), comprising a plurality of sub-pixel areas, (Figures 4-5 #105a-d), arranged in an array, and a first area between adjacent sub-pixel areas, (Figures 4-5 #105a-d); a plurality of scanning lines, (Figures 4-5 #101a-b), at a side of the base substrate, (Figures 4-5 #100), and in the first area; wherein the plurality of scanning lines, (Figures 4-5 #101a-b), extend in a first direction, and are arranged in a second direction, the first direction intersects with the second direction; a plurality of first pixel electrodes, (Figures 4-5 #105a-d), at a side of the scanning line, (Figures 4-5 #101a-b), facing away from the base substrate, (Figures 4-5 #100); wherein each of the plurality of first pixel electrodes, (Figures 4-5 #105a-d), comprises: a first portion, (Figure 4a area of #105a that overlaps #101a); and a second portion, (Figure 4a area of #105a above #101a), and a third portion, (Figure 4a area of #105a below #101a), at two sides of the first portion, (Figure 4a area of #105a that overlaps #101a), in the second direction; wherein an orthographic projection of the first portion, (Figure 4a area of #105a that overlaps #101a), on the base substrate, (Figures 4-5 #100), and an orthographic projection of the scanning line, (Figures 4-5 #101a), on the base substrate, (Figures 4-5 #100), have an overlapping area; and an orthographic projection of the second portion, (Figure 4a area of #105a above #101a), on the base substrate, (Figures 4-5 #100), and an orthographic projection of the third portion, (Figure 4a area of #105a below #101a), on the base substrate, (Figures 4-5 #100), are arranged at two sides of the scanning line, (Figures 4-5 #101a), respectively.
2. Referring to claim 34, Kim et al. teaches the array substrate according to claim 33, further comprising: a plurality of first thin-film transistors, (Figures 4-5 #TFT), in the first area and at a side of the base substrate, (Figures 4-5 #100), same as the scanning line; wherein the first thin-film transistor, (Figures 4-5 #TFT), comprises a first electrode, (Figures 4-5 #111), a second electrode, (Figures 4-5 #103a), and a third electrode, (Figures 4-5 #115b); the first electrode, (Figures 4-5 #111), is electrically connected with the scanning line, (Figures 4-5 #101a), and the third electrode, (Figures 4-5 #115b), is electrically connected with the first pixel electrode, (Figures 4-5 #105a); wherein, in the second direction, the third electrode, (Figures 4-5 #115b), of the first thin-film transistor, (Figures 4-5 #TFT), and the third portion, (Figure 4a area of #105a below #101a), are arranged at the same side of the scanning line, (Figures 4-5 #101a), connected with the first thin-film transistor, (Figures 4-5 #TFT); the orthographic projection of the third portion, (Figure 4a area of #105a below #101a), on the base substrate, (Figures 4-5 #100), and an orthographic projection of the third electrode, (Figures 4-5 #115b), on the base substrate, (Figures 4-5 #100), have an overlapping area; and the third portion, (Figure 4a area of #105a below #101a), is electrically connected with the third electrode, (Figures 4-5 #115b).
3. Referring to claim 35, Kim et al. teaches the array substrate according to claim 34, wherein the third electrode, (Figures 4-5 #115b), comprises a first strip portion, (Figures 4-5 #115b), extending in the first direction, and the third portion, (Figure 4a area of #105a below #101a), comprises a second strip portion, (Figure 4a area of #105a below #101a that has a strip shape when drawn out or a portion that is selected to define the shape of a strip, since the limitation “portion’ is read in its broadest reasonable interpretation), extending in the first direction; and an orthographic projection of the second strip portion, (Figure 4a area of #105a below #101a that has a strip shape when drawn out or a portion that is selected to define the shape of a strip, since the limitation “portion’ is read in its broadest reasonable interpretation), on the base substrate, (Figures 4-5 #100), and an orthographic projection of the first strip portion, (Figures 4-5 #115b), on the base substrate, (Figures 4-5 #100), have an overlapping area.
4. Referring to claim 36, Kim et al. teaches the array substrate according to claim 35, wherein the orthographic projection of the second strip portion, (Figure 4a area of #105a below #101a that has a strip shape when drawn out or a portion that is selected to define the shape of a strip, since the limitation “portion’ is read in its broadest reasonable interpretation), on the base substrate, (Figures 4-5 #100), covers the orthographic projection of the first strip portion, (Figures 4-5 #115b), on the base substrate, (Figures 4-5 #100).
5. Referring to claim 37, Kim et al. teaches the array substrate according to claim 36, wherein the second strip portion, (Figure 4a area of #105a below #101a that has a strip shape when drawn out or a portion that is selected to define the shape of a strip, since the limitation “portion’ is read in its broadest reasonable interpretation), wraps around a side surface of the first strip portion, (Figures 4-5 #115b).
6. Referring to claim 38, Kim et al. teaches the array substrate according to claim 35, wherein at least one of following is comprised: the orthographic projection of the third portion, (Figure 4a area of #105a below #101a), on the base substrate, (Figures 4-5 #100), and an orthographic projection of the first electrode, (Figures 4-5 #111), on the base substrate, (Figures 4-5 #100), do not overlap with each other; or in the first direction, the second portion, (Figure 4a area of #105a above #101a), and a third portion, (Figure 4a area of #105a below #101a), are respectively arranged at two sides of the first portion, (Figure 4a area of #105a that overlaps #101a).
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
7. Claims 39-52 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
8. The prior art teaches the claimed matter in the rejections above, but is silent with respect to the above teachings in combination with the array substrate according to claim 35, wherein the plurality of sub-pixel areas are divided into a plurality of sub-pixel area columns, and the plurality of sub-pixel area columns extend in the second direction and are arranged in the first direction; the orthographic projection the first strip portion on the base substrate passes through an area between two adjacent sub-pixel area columns; in the first pixel electrode and the first thin-film transistor electrically connected with each other, the first electrode and the second portion correspond to two different sub-pixel area columns that adjacent to each other, respectively; and/or a display panel, comprising: the array substrate according to claim 33; an opposing substrate, arranged opposite to the array substrate; and a liquid crystal layer, arranged between the array substrate and the opposing substrate; wherein the plurality of scanning lines comprised in the array substrate comprise a plurality of second widening portions; the opposing substrate comprises a plurality of spacers; and an orthographic projection of the spacer on the base substrate comprised in the array substrate is located within an orthographic projection of the second widening portion on the base substrate.
Conclusion
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/VICTOR A MANDALA/Primary Examiner, Art Unit 2899 7/14/26
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