DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on 2/13/2026 has been entered and considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 19 and 20 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 19 recites that the effective level of second scanning signal terminal comprises “seventh” effective level and “eighth” effective level. The new claim limitation recites that the time period of the effective level of the compensation control signal is longer than the time period of the effective level of the second scanning signal termina. However, the claim language does not specifically define whether the effective level of the second scanning signal is time period of the seventh effective level, the eighth effective level or the combined time period of seventh effective and eighth effective level.
Claim 20 is rejected as being dependent on rejected base claim 19. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 19 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Son et al (PGPUB 2021/0375193 A1).
As to claim 19, Son (Figs. 3-5) teaches, a pixel circuit (pixel 10), comprising:
a light-emitting device (light emitting device LD)(¶75);
a driving transistor (first transistor M1/ driving transistor) configured to generate a driving current that drives the light-emitting device to emit light according to a data voltage (data voltage, ¶ 64, 82)(¶ 78: i.e. based on node N1);
a light-emitting control circuit (emission driver 300) coupled with the driving transistor, and configured to, in response to an effective level (i.e. low level in Fig. 4) of a light-emitting control signal terminal (emission control line Ei)(i.e. Ei turns on M5, which allows current through transistor M1), provide the driving current generated by the driving transistor to the light-emitting device, and drive the light-emitting device to emit light (¶ 78, 84);
a functional circuit (transistor M4 and M8) coupled with the driving transistor, and configured to, in response to a plurality of effective levels (i.e. low levels in Fig. 4) that occur at intervals between second scanning signal terminals (i.e. intervals of S1i in P1 and P4 in the course of multiple frames), operate in a data refresh phase (display scan period DSP)(¶ 100, 101); and
a threshold compensation circuit (third transistor M3) coupled with the driving transistor (Fig. 3), configured to, in response to an effective level (i.e. high level as shown in Fig. 4) of a compensation control signal terminal (second scan line S2i)(¶ 80), input a threshold voltage (turn-on voltage) of the driving transistor into a gate (i.e. gate connected to node N3) of the driving transistor (¶ 69: scan signal sets the transistors to be in a turn-on state);
wherein in the data refresh phase, a time period (i.e. Periods P1 to P5, which is the time period of Ei at high level in Fig. 4) of an invalid level (high level) of the light-emitting control signal terminal comprises a time period (i.e. period P1 and P3) of an effective level (i.e. high level) of the compensation control signal terminal (i.e. M3 turns on with high level during P1 and P3) and a time period (i.e. period of P1 and P4) of an effective level (i.e. low level) of the second scanning signal terminal (i.e. S1i is applied during the period when Ei is at high level), the effective level of the second scanning signal terminal comprises at least one seventh effective level (i.e. low level of S1i during P1 reads on “one seventh effective level” which is named in the specification as one of effective levels) and at least one eighth effective level (i.e. low level of S1i during P4 reads on “one eight effective level” which is named in the specification as another one of effective levels), and the time period of the effective level of the compensation control signal terminal does not overlap with a time period of the at least one eighth effective level (Fig. 4: i.e. high level of S2i in P3 do not overlap with low level of S1i in P4),
wherein the time period of the effective level of the compensation control signal terminal is longer than the time period of the effective level of the second scanning signal terminal (Fig. 4: i.e. the durations of the high level of S2i during P1 and P3 are longer than the duration of low level of S1i during P1, P4. Further, each duration of high level of S2i is longer than the combined duration of low level of S1i in P1 and P4 as shown in Fig. 4).
As to claim 20, Son (Figs. 4, 5) teaches, wherein the time period of the effective level of the compensation control signal terminal comprises a time period of the seventh effective level (i.e. high level of S1i in S1); and/or
wherein in the data refresh phase, the time period of the at least one eighth effective level occurs before or after the time period of the effective level of the compensation control signal terminal (Fig. 4: i.e. low level S1i in P4 occurs after high level S2i).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 4, 5, 11, 22, 28 and 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Son in view of Han (PGPUB 2011/0193855 A1).
As to claim 1, Son (Figs. 3-5) teaches, a pixel circuit (pixel 10), comprising:
a light-emitting device (light emitting device LD)(¶ 75);
a driving transistor (first transistor M1/ driving transistor) configured to generate a driving current that drives the light-emitting device to emit light according to a data voltage (data voltage, ¶ 64, 82), and configured to write data signals into a gate of the driving transistor (¶ 78: i.e. based on node N1);
a light-emitting control circuit (emission driver 300) coupled with the driving transistor, and configured to, in response to an effective level (i.e. low level in Fig. 4) of a light-emitting control signal terminal (emission control line Ei)(i.e. Ei turns on M5, which allows current through transistor M1), provide the driving current generated by the driving transistor to the light-emitting device, and drive the light-emitting device to emit light (¶ 78, 84);
a data-writing circuit (second transistor M2) coupled with a first electrode (i.e. upper electrode of M1 as shown in Fig. 3) of the driving transistor, and configured to operate in a data refresh phase (display scan period DSP) in response to a plurality of effective levels (i.e. low level in Fig. 4) that occur at intervals between first scanning signal terminals (Fig. 4, ¶ 72: i.e. sequentially supply the fourth scan signals S4i); and
a threshold compensation circuit (third transistor M3) coupled with the driving transistor (Fig. 3), configured to, in response to an effective level (i.e. high level as shown in Fig. 4) of a compensation control signal terminal (second scan line S2i)(¶ 80), input a threshold voltage (turn-on voltage) of the driving transistor into the gate (i.e. gate connected to node N3) of the driving transistor (¶ 69: scan signal sets the transistors to be in a turn-on state);
wherein in the data refresh phase, a time period (first non-emission period NEP) of an invalid level of the light-emitting control signal terminal comprises a time period (first period P1 and third period P3, ¶ 80, 105, 114: i.e. M3 turned on by high logic of S2i) of the effective level of the compensation control signal terminal and a time period (i.e. low logic of S4i in third period P3 as shown in Fig. 4) of an effective level of the first scanning signal terminal (Fig. 4, ¶ 53), and
the time period of the effective level of the compensation control signal terminal comprises a time period of the first effective level (i.e. during P3, S2i is at high logic to turn on M3 and S4i is at low logic to turn on M2),
wherein the time period of the effective level of the compensation control signal terminal is longer than the time period of the effective level of the first scanning signal terminal (Fig. 4: i.e. the durations of high level of S2i in P1 or P3 are longer than the duration of low level of S4i in P3).
Son teaches the pixel circuit of claim 1, but does not specifically teach the effective level of the first scanning signal terminal comprises at least one first effective level and at least one second effective level.
Han (Figs. 8, 9) teaches, the effective level of the first scanning signal terminal (scan lines SCAN[N]) comprises at least one first effective level and at least one second effective level (Fig. 9: i.e. periods T22 – T27, each period with low logic SCAN is considered as one effective level, see ¶ 186 which is the same way as applicant disclosed two effective levels Ga as shown in Fig.3).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Han’s scan signal pattern into Son’s pixel, so as to compensate threshold voltage (¶ 186).
As to claim 2, Son (Figs. 3, 4) teaches, wherein in the data refresh phase, a time period of the at least one second effective level occurs after the time period of the effective level of the compensation control signal terminal (Fig. 4: i.e. S4i low logic happens after period P1, which includes high logic of S2i).
Son does not specifically teach a plurality of first and second effective levels.
Han (Fig. 9) teaches, the first effective level and the second effective level (Fig. 9: i.e. four pulses of SCAN),
wherein in the data refresh phase, a time period of the at least one second effective level occurs before the time period of the effective level of the compensation control signal terminal (Fig. 9: i.e. first SCAN pulse occurs before second SCAN pulse. Any of the SCAN pulses can be interpreted as the first or second effective level and the compensation control signal since TR1 and SW1 all receive input from SCAN).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Han’s scan signal pattern into Son’s pixel, so as to compensate threshold voltage (¶ 186).
As to claim 4, Son (Figs. 3, 4) teaches, a first initialization circuit (fourth transistor M4)(¶ 81),
wherein the first initialization circuit is coupled with the first electrode of the driving transistor (Fig. 3: i.e. M1, N1 and M4 are connected);
the first initialization circuit is configured to, in response to at least one effective level of a first reset control signal terminal (first scan signal from S1i) in the data refresh phase, provide a signal (first power source VEH) of the first initialization signal terminal to the first electrode of the driving transistor (¶ 81);
wherein in the data refresh phase, the time period of the invalid level of the light-emitting control signal terminal further comprises a time period (first period P1) of the effective level of the first reset control signal terminal (Fig. 4: i.e. W2 is low level during NEP), and the time period of the effective level of the first reset control signal terminal does not overlap with a time period of a plurality of effective levels of the first scanning signal terminal (Fig. 4: i.e. scan signal S4i is low level during P3 and not overlap low levels of S1i in P1 and P4).
As to claim 5, Son (Figs. 3, 4) teaches, wherein the effective level of the first reset control signal terminal comprises at least one third effective level;
in the data refresh phase, a time period of the at least one third effective level occurs after the time period of the plurality of effective levels of the first scanning signal terminal; and/or (i.e. due to “or” clause, Son teaches following limitations and reads on claim 5)
wherein the effective level of the first reset control signal terminal comprises at least one fourth effective level (i.e. low logic during W2 in Fig. 4);
in the data refresh phase, the time period of the effective level of the compensation control signal terminal comprises a time period (W2) of the fourth effective level (Fig. 4: i.e. low logic of S1i during W2 and high logic of S2i overlap), and the time period of the fourth effective level occurs before a time period of the first effective level of the first scanning signal terminal (Fig. 4: i.e. W2 occurs before low logic of S4i).
As to claim 11, Son (Figs. 3, 4) teaches, comprising a third initialization circuit (eighth transistor M8)(Fig. 3),
wherein the third initialization circuit is coupled with the light-emitting device (Fig. 3: i.e. coupled via node N4);
the third initialization circuit is configured to, in response to an effective level of a third reset control signal terminal (first scan signal S1i), provide a signal (third power source Vint2) of the third initialization signal terminal to the light-emitting device (¶ 88);
wherein one of the compensation control signal terminal, the first scanning signal terminal, a first reset control signal terminal (i.e. S1i as discussed above), a second reset control signal terminal is a signal terminal same as the third reset control signal terminal (Fig. 3: i.e. M4 and M8 both receive S1i to apply VEH and Vint2 to corresponding nodes respectively).
As to claim 22, Son (Figs. 3-5) teaches, a display panel (display device 1000) comprising a plurality of a pixel circuit (pixel 10); each of the plurality of sub-pixels comprises a pixel circuit (pixel 10), wherein the pixel circuit comprises:
a light-emitting device (light emitting device LD)(¶ 75);
a driving transistor (first transistor M1/ driving transistor) configured to generate a driving current that drives the light-emitting device to emit light according to a data voltage (data voltage, ¶ 64, 82)(¶ 78: i.e. based on node N1);
a light-emitting control circuit (emission driver 300) coupled with the driving transistor, and configured to, in response to an effective level (i.e. low level in Fig. 4) of a light-emitting control signal terminal (emission control line Ei)(i.e. Ei turns on M5, which allows current through transistor M1), provide the driving current generated by the driving transistor to the light-emitting device, and drive the light-emitting device to emit light (¶ 78, 84);
a data-writing circuit (second transistor M2) coupled with a first electrode (i.e. upper electrode of M1 as shown in Fig. 3) of the driving transistor, and configured to operate in a data refresh phase (display scan period DSP) in response to a plurality of effective levels (i.e. low level in Fig. 4) that occur at intervals between first scanning signal terminals (Fig. 4, ¶ 72: i.e. sequentially supply the fourth scan signals S4i); and
a threshold compensation circuit (third transistor M3) coupled with the driving transistor (Fig. 3), configured to, in response to an effective level (i.e. high level as shown in Fig. 4) of a compensation control signal terminal (second scan line S2i)(¶ 80), input a threshold voltage (turn-on voltage) of the driving transistor into a gate (i.e. gate connected to node N3) of the driving transistor (¶ 69: scan signal sets the transistors to be in a turn-on state);
wherein in the data refresh phase, a time period (first non-emission period NEP) of an invalid level of the light-emitting control signal terminal comprises a time period (first period P1 and third period P3, ¶ 80, 105, 114: i.e. M3 turned on by high logic of S2i) of the effective level of the compensation control signal terminal and a time period (i.e. low logic of S4i in third period P3 as shown in Fig. 4) of an effective level of the first scanning signal terminal (Fig. 4, ¶ 53), and the time period of the effective level of the compensation control signal terminal comprises a time period of the first effective level (Fig. 4: i.e. high levels of S2i in periods P1 and P3),
wherein the time period of the effective level of the compensation control signal terminal is longer than the time period of the effective level of the first scanning signal terminal (Fig. 4: i.e. the durations of high level of S2i in P1 or P3 are longer than the duration of low level of S4i in P3).
Son teaches the pixel circuit of claim 1, but does not specifically teach the effective level of the first scanning signal terminal comprises at least one first effective level and at least one second effective level.
Han (Figs. 8, 9) teaches, the effective level of the first scanning signal terminal (scan lines SCAN[N]) comprises at least one first effective level and at least one second effective level (Fig. 9: i.e. periods T22 – T27, each period with low logic SCAN is considered as one effective level)(¶ 186).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Han’s scan signal pattern into Son’s pixel, so as to compensate threshold voltage (¶ 186).
As to claim 28, Son (Figs. 3-5) teaches, comprising:
the data refresh phase; wherein the data refresh phase comprises:
in a data threshold compensation phase (periods P3), operating, by the data-writing circuit, in response to a first effective level (i.e. low level) of the first scanning signal terminal (i.e. S4i turns on at S4i), and inputting, by the threshold compensation circuit, the threshold voltage of the driving transistor into the gate of the driving transistor in response to the effective level of the compensation control signal terminal (¶ 69: scan signal sets the transistors to be in a turn-on state),
in a light-emitting stage (emission period EP, EP1-4), providing, by the light-emitting control circuit, the driving current generated by the driving transistor to the light-emitting device to drive the light-emitting device to emit light in response to the effective level of the light-emitting control signal terminal (¶ 84: i.e. M5 and M6 turn on in response to Ei, and Ei is active during EP as shown in the figures).
Son does not specifically teach the second effective level of the first scanning terminal.
Han (Fig. 9) teaches, data threshold compensation phase (T22)(Fig. 9)
in a first initialization auxiliary phase (T24), operating, by the data-writing circuit, in response to the second effective level of the first scanning signal terminal (Fig. 9: i.e. second turn-on pulse for SCAN).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Han’s scan signal pattern into Son’s pixel, so as to compensate threshold voltage (¶ 186).
As to claim 29, Son (Figs. 3-5) teaches, comprising:
in a data threshold compensation phase (periods P3), operating, by the data-writing circuit, in response to a first effective level (i.e. low level) of the first scanning signal terminal (i.e. S4i turns on at S4i), and inputting, by the threshold compensation circuit, the threshold voltage of the driving transistor into the gate of the driving transistor in response to the effective level of the compensation control signal terminal (¶ 69: scan signal sets the transistors to be in a turn-on state),
in a light-emitting stage (emission period EP, EP1-4), providing, by the light-emitting control circuit, the driving current generated by the driving transistor to the light-emitting device to drive the light-emitting device to emit light in response to the effective level of the light-emitting control signal terminal (¶ 84: i.e. M5 and M6 turn on in response to Ei, and Ei is active during EP as shown in the figures).
Son does not teach a second initialization auxiliary phase.
Han (Fig. 9) teaches, in a second initialization auxiliary phase (T25 and 26), operating, by the data-writing circuit, in response to the second effective level of the first scanning signal terminal (Fig. 9: i.e. T25, 26 is applied after T24).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Han’s scan signal pattern into Son’s pixel, so as to compensate threshold voltage (¶ 186).
Claim(s) 7, 8, 10 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Son and Han as applied to claim 1 above, and further in view of Nam et al (PGPUB 2019/0206320 A).
As to claim 7, Son and Han teach the pixel circuit of claim 1 but do not specifically teach a second initialization circuit.
Nam (Figs. 1, 3) teaches, a second initialization circuit (second initialization circuit TI2)(Fig. 1),
wherein the second initialization circuit is coupled with a second electrode (i.e. lower terminal of driving transistor TD) of the driving transistor (Fig. 1);
the second initialization circuit is configured to, in response to at least one effective level of a second reset control signal terminal (i.e. low level applied on initialization control signal ICS), provide a signal (initialization signal VINT) of a second initialization signal terminal (TI12) to the second electrode of the driving transistor (Fig. 1, ¶ 44);
wherein in the data refresh phase (periods P1-P3 in Fig. 3), the time period of the invalid level of the light-emitting control signal terminal (i.e. duration of EM shown as high level in Fig. 3) comprises a time period (period P1) of the effective level of the second reset control signal terminal (Fig. 3: i.e. ICS is at low level during high level of EM), and the time period of the effective level of the second reset control signal terminal does not overlap with a time period of a plurality of effective levels in the first scanning signal terminal (Fig. 3: i.e. low level of ICS do not overlap with low level of SS).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Nam’s pixel structure and driving method into Son’s pixel as modified with the teaching of Han, so as to improve display quality (¶ 4, 5) and leakage current (¶ 25).
As to claim 8, Son and Han teach the pixel circuit of claim 7, but do not specifically teach the second reset control signal terminal.
Nam (Figs. 1, 3) teaches, wherein the effective level of the second reset control signal terminal comprises at least one fifth effective level (i.e. low level of ICS during P1)(Fig. 3);
in the data refresh phase, the time period of the effective level of the compensation control signal terminal comprises a time period of the at least one fifth effective level (Fig. 3: i.e. when SS2 is at low level, ICS is at low level), and the time period of the at least one fifth effective level occurs before a time period of at least one first effective level of the first scanning signal terminal (SS1)(Fig. 3: i.e. low level of ICS occurs before low level of SS1).
Nam does not specifically teach the timing of a fourth effective level. However, Son, Han and Nam combination would necessarily teach this limitation. Son teaches on Fig. 4 that the time period of the first effective level of the first scanning signal terminal (S1i) occurs after low level S4i, which is the scan signal for turning on the pixel in Son. Nam’s low level ICS occurs before the time period of low level SS1, which is the scan signal for turning on the pixel in Nam.
Therefore, Son, Han and Nam prior arts teach, wherein in the data refresh phase, the time period of the fifth effective level occurs before or after a time period of a fourth effective level of a first reset control signal terminal (i.e. low level ICS is before effective level of the scan signal in Nam, and low level S1i is after the scan signal in Son. Therefore, in combination, the time period of ICS, the fifth effective level, must be necessarily before the time period of S1i, the first reset control signal terminal).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Nam’s pixel structure and driving method into Son’s pixel as modified with the teaching of Han, so as to improve display quality (¶ 4, 5) and leakage current (¶ 25).
As to claim 10, Son and Han teach the pixel circuit of claim 7 but do not specifically teach the second reset control signal terminal.
Nam (Figs. 2B) teaches, wherein the effective level of the second reset control signal terminal comprises at least one sixth effective level (low level ICS in P1 that do not overlap with low level of SS);
in the data refresh phase, a time period of the at least one sixth effective level occurs after or before the time period of the effective level of the compensation control signal terminal i.e. Nam teaches another embodiment with low level ICS being applied before the time period of T3 is turned off).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Nam’s pixel structure and driving method into Son’s pixel as modified with the teaching of Han, so as to improve display quality (¶ 4, 5) and leakage current (¶ 25).
As to claim 18, Son (Figs. 3, 4) teaches, wherein the data-writing circuit comprises a first transistor (second transistor M2)(¶ 95);
a gate (i.e. gate of M2) of the first transistor is coupled with the first scanning signal terminal (i.e. S4i), a first electrode (i.e. left terminal as shown in Fig. 3) of the first transistor is coupled with a data signal terminal (data line Dj), and a second electrode (i.e. right terminal) of the first transistor is coupled with the first electrode of the driving transistor (Fig. 3: i.e. M2 connects to M1 via N1);
the threshold compensation circuit comprises a second transistor (third transistor M3) and a storage capacitor (storage capacitor Cst)(¶ 94);
a gate (i.e. gate of M3) of the second transistor is coupled with the compensation control signal terminal (i.e. S2i), a first electrode (i.e. left terminal of M3 as shown in Fig. 3) of the second transistor is coupled with the gate of the driving transistor, a second electrode (i.e. right terminal) of the second transistor is coupled with a second electrode (i.e. lower terminal of M1 via node N2) of the driving transistor (Fig. 3);
a first electrode plate (i.e. lower terminal of Cst as shown in Fig. 3) of the storage capacitor is coupled with the gate of the driving transistor (i.e. connects to gate of M1 via N3), and a second electrode plate (i.e. upper terminal) of the storage capacitor is coupled with a first power supply terminal (first driving power source VDD)(Fig. 3);
the light-emitting control circuit comprises a third transistor (fifth transistor M5) and a fourth transistor (sixth transistor M6)(¶ 84, 85, 113);
a gate (i.e. gate of fifth transistor M5) of the third transistor is coupled with the light-emitting control signal terminal (emission control line Ei), a first electrode (i.e. upper terminal of M5) of the third transistor is coupled with the first power supply terminal, a second electrode (i.e. lower terminal) of the third transistor is coupled with the first electrode of the driving transistor, a gate (i.e. gate of M6) of the fourth transistor is coupled with the light-emitting control signal terminal, a first electrode (i.e. upper terminal of M6) of the fourth transistor is coupled with the second electrode of the driving transistor, and a second electrode (i.e. lower terminal) of the fourth transistor is coupled with the light-emitting device (Fig. 3);
a first initialization circuit (fourth transistor M4) comprises a fifth transistor (M4), a gate (i.e. gate of M4) of the fifth transistor is coupled with the first reset control signal terminal (i.e. connects to S1i), a first electrode (i.e. lower terminal as shown in Fig. 3) of the fifth transistor is coupled with the first initialization signal terminal, and a second electrode (i.e. upper terminal as shown in Fig. 3) of the fifth transistor is coupled with the first electrode of the driving transistor (Fig. 3: i.e. M4 connects to M1 via N1);
a third initialization circuit (eighth transistor M8) comprises a seventh transistor (M8); a gate (i.e. gate of M8) of the seventh transistor is coupled with a third reset control signal terminal (i.e. connects to S1i), a first electrode (i.e. left terminal as shown in Fig. 8) of the seventh transistor is coupled with a third initialization signal terminal (Vint2), and a second electrode (i.e. right terminal of M8) of the seventh transistor is coupled with the light-emitting device (Fig. 3).
Son and Han do not specifically teach a second initialization circuit.
Nam (Fig. 1) teaches, a second initialization circuit (second initialization transistor TI2) comprises a sixth transistor (TI2), a gate of the sixth transistor is coupled with a second reset control signal terminal (i.e. gate of TI2 is connected to ICS), a first electrode (i.e. lower terminal of TI2) of the sixth transistor is coupled with a second initialization signal terminal (i.e. connects to VINIT via TI1), and a second electrode (i.e. upper terminal) of the sixth transistor is coupled with the second electrode of the driving transistor (Fig. 1: i.e. connects to lower terminal of TD).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Nam’s pixel structure and driving method into Son’s pixel as modified with the teaching of Han, so as to improve display quality (¶ 4, 5) and leakage current (¶ 25).
Claim(s) 13, 15-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Son and Han as applied to claim 1 above, and further in view of Zhang (USPAT 11,538,412 B1).
As to claim 13, Son (Fig. 5) teaches, wherein a display frame corresponding to the pixel circuit comprises a refresh sub-frame (Fig. 5: DSP and BSP) and a maintaining sub-frame (BSP), and an operation of the pixel circuit in the refresh sub-frame (DSP) is an operation of the pixel circuit in the data refresh phase (Fig. 5);
wherein the compensation control signal terminal comprises an invalid level in the maintaining sub-frame (i.e. M3 is a N-type transistor, which stays off during BSP in response to low-level S2i)(Fig.5);
the light-emitting control signal terminal comprises an invalid level and an effective level in at least one maintaining sub-frame (Fig. 5: i.e. Ei turns on M5 and M6 with low logic during EP2-EP4 and turns off with high logic during NEP2-NEP4).
Son and Han do not teach, the first scanning signal terminal comprises an invalid level and an effective level in at least one maintaining sub-frame.
Zhang (Figs. 4, 10, 11) teaches, the first scanning signal terminal (control signal S1) comprises an invalid level (i.e. low level) and an effective level (i.e. high level) in at least one maintaining sub-frame (holding frame).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Zhang’s driving method for holding period into Sol’s pixel circuit as modified with the teaching of Han, so as to improve visual experience (col. 10 lines 19-32).
As to claim 15, Son (Fig. 5) teaches, wherein a first reset control signal terminal (S1i) comprises an invalid level and an effective level in at least one maintaining sub-frame (Fig. 5: i.e. high and low levels during BSP); or
a first reset control signal terminal comprises an invalid level in the maintaining sub-frame (Fig. 5: i.e. high logic during BSP).
As to claim 16, Son and Han teach the pixel circuit but do not teach the second reset control signal termina.
Zhang (Fig. 4) teaches, wherein a second reset control signal terminal (control signal SR) comprises an invalid level (high level) and an effective level (low level) in at least one maintaining sub-frame (i.e. during holding frame in Fig. 11); or
a second reset control signal terminal comprises an invalid level (i.e. high level) in the maintaining sub-frame(i.e. during holding frame in Fig. 11).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Zhang’s driving method for holding period into Sol’s pixel circuit as modified with the teaching of Han, so as to improve visual experience (col. 10 lines 19-32).
As to claim 17, Son (Figs. 3, 5) teaches, wherein a third reset control signal terminal (i.e. terminal of M8 receiving S1i) comprises an invalid level and an effective level in at least one maintaining sub-frame (Fig. 5: i.e. S1i is at high and low levels in BSP); or
a third reset control signal terminal comprises an invalid level in the maintaining sub-frame (Fig. 5: i.e. S1i is at high and low levels in BSP).
Allowable Subject Matter
Claims 23 and 24 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Applicant’s claimed invention regards an OLED pixel comprising a plurality of initialization transistors and a threshold compensation transistor that connects the lower terminal of the driving transistor and the gate terminal of the driving transistor. The driving method of the pixel includes a plurality of scan signals being applied to the writing transistor, which connects the driving transistor and the data line. The plurality of scan signals are shown as first scanning signal terminal GA as shown in Fig. 3. Regarding this, Applicant claims the structure of the pixel in claim 1 and further require that the timing of one pulse of the plurality of scan signals in first row of scanning line to overlap with the timing another pulse of the plurality of scan signals in another row of scanning line.
Claim 23 specifically claims the limitation, “… a time period of the second effective level corresponding to a pixel circuit in a nth row of sub-pixels overlaps with a time period of the first effective level corresponding to a pixel circuit in a (n+m)th row of sub-pixels”.
Claim 24 specifically claims the limitation, “… a time period of the second effective level corresponding to a pixel circuit in a qth row of sub-pixels overlaps with a time period of the first effective level corresponding to a pixel circuit in a (q-k)th row of sub-pixels”.
Examiner conducted a search to find the prior arts that would teach these limitations but could not find them. None of the prior arts alone or in combination teach the structural limitation required in claim 1 and the driving timing as required in claims 23 and 24.
Response to Arguments
Applicant's arguments filed 2/13/2026 have been fully considered but they are not persuasive.
Applicant has amended claims 1, 19 and 22 to recite the new limitations. Claims 1 and 22 recite the new limitation, “wherein the time period of the effective level of the compensation control signal terminal is longer than the time period of the effective level of the first scanning signal terminal”. Claim 19 recites the limitation, “wherein the time period of the effective level of the compensation control signal terminal is longer than the time period of the effective level of the second scanning signal terminal”. Applicant further argues that Son’s light-emitting driver 300 does not correspond to the light emitting control circuit recited in claim 1 of the present application. Examiner respectfully disagrees. In Applicant’s invention, light-emitting driver circuit provides current to the pixel by outputting emission control signal EM via EML as shown in Figs. 2 and 28. This operation is identical to the Son prior art, which provides current through the driving transistor by providing emission control signals through emission control lines Ei to turn on the transistors M5 and M6. Further, Applicant argues that Han prior art does not teach the new limitations. However, Son prior art teaches these limitations. For further detail, please refer to the discussion above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANGHYUK PARK whose telephone number is (571)270-7359. The examiner can normally be reached on 10:00AM - 6:00 M-F.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached on ((571) 272-7772. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/SANGHYUK PARK/Primary Examiner, Art Unit 2623
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