DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 15 July 2024 complies with the provisions of 37 CFR 1.97. Accordingly, the examiner has considered the information disclosure statement.
Drawings
The drawings submitted have been reviewed and determined to facilitate understanding of the invention. The drawings are accepted as submitted.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-8, 10, and 14 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1, 10, and 14 each recite the limitation "the outside" in lines 9, 3, and 9, respectively. There is insufficient antecedent basis for this limitation in the claim.
For examination purposes, “the outside” will be considered to refer to a structure not formed in or on the optical system-in-package or module.
Claims 2-8 depend from Claim 1 and are therefore indefinite for the same reasons.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5 and 9-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Patent Application Publication US 2016/0141279 A1 to Krabe et al. (“US1”), cited in Applicant’s IDS.
Regarding Claim 1, US1 describes an optical system-in-package (O-SIP) (see Fig 3, 5-9) comprising:
a mold body (37) having a first surface and a second surface which are flat on a lower portion and an upper portion of the mold body, respectively;
a photonic integrated circuit (IC) (2, 30) molded inside the mold body to expose a bonding pad (32, 51a) on the second surface;
an electronic IC (20) molded to be spaced apart from the photonic IC inside the mold body to expose the bonding pad on the second surface; and
a redistribution layer (RDL) (121a) formed on the second surface of the mold body and having a plurality of fan-out terminal pads electrically connected to the outside while interconnecting the photonic IC and the electronic IC.
Regarding Claim 2, US1 describes the photonic IC comprising at least one of a light emitting device, a light receiving device, a chip that provides an additional function to the light emitting device or the light receiving device or is in charge of signal processing, and a planar lightwave circuit (PLC) (see [0052]).
Regarding Claim 3, US1 describes electronic IC comprising one of a driving circuit for driving the light emitting device, a circuit that receives and amplifies and/or converts an electrical signal from the light receiving device, a laser diode (LD) driver IC, a clock data recovery (CDR), an equalizer, a transimpedance amplifier (TIA), an inter-integrated circuit (I2C) communication, and a Digital Signal Processing (DSP) (see [0052]).
Regarding Claim 4, US1 describes (first and second metal structures (133) for heat dissipation (see [0067]), in which upper surfaces of the first and second metal structures are bonded to lower portions of the photonic IC and the electronic IC and lower surfaces thereof are exposed, respectively (see Fig 5.
Regarding Claim 5, US1 describes:
a third metal structure (10) for a via that is inserted through the mold body between the photonic IC and the electronic IC, has an upper end connected to the RDL and a lower end portion exposed (see Fig 5); and
a metal connection layer that connects the RDL to the lower portions of the photonic IC and the electronic IC and has a lower surface of the metal connection layer exposed by interconnecting the lower surfaces of the first to third metal structures (see [0048]).
Regarding Claim 9, US1 describes an optical module (100, see Figs 3, 5) comprising:
an optical system-in-package (O-SIP) for generating an optical signal or receiving an optical signal, in which a photonic integrated circuit (IC) (2, 30) and an electronic IC (20) for driving or interfacing the photonic IC are molded inside a mold body (37) having a first surface and a second surface which are flat, on a lower portion and an upper portion of the mold body; and
a printed circuit board (PCB) (70) in which the O-SIP is mounted on a lower surface of the PCB and multiple electronic components are mounted on an upper surface thereof to control transmission and reception of the O-SIP (see Fig 3, [0052]), wherein
the PCB comprises a through hole (72, 73) forming an optical path when generating or receiving an optical signal in a vertical direction from or to the photonic IC in a portion corresponding to a light entrance/exit part of the photonic IC.
Regarding Claim 10, US1 describes a redistribution layer (RDL) (42) having a plurality of fan-out terminal pads for electrically connecting the photonic IC and the electronic IC to the outside while interconnecting the photonic IC and the electronic IC on the second surface in which a light entrance/exit part of the photonic IC is arranged (see [0053]).
Allowable Subject Matter
Claim 6-8 and 14 would be allowable if rewritten to overcome the rejection under 35 U.S.C. 112(b) set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claim 11 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 12 and 13 are allowed.
Claim 6 describes a thermal interface material (TIM) installed on a lower portion of the metal connection layer to form a heat dissipation path to a metal housing of the main body.
Claim 7 describes a transmitter optical sub-assembly (TOSA) to which a light emitting device is applied as the photonic IC and a receiver optical sub-assembly (ROSA) to which a light receiving device is applied as the photonic IC are formed in the O-SIP.
Claim 8 describes a metasurface that serves as a microlens or a metalens formed through a microelectro mechanical system (MEMS) or an imprint process on the RDL located above the light entrance/exit part.
Claim 11 describes an optical component positioned above the through hole of the PCB to bend the optical path 90 degrees from vertically to horizontally to transmit the optical signal between an optical fiber and the photonic IC.
Claim 12 describes an arrayed waveguide grating (AWG), including a tip portion having an inclined surface, which is coupled with an end portion of the coupling groove, the AWG performing, when optical signals of a plurality of channels generated from the photonic IC are received, a wavelength division multiplexing (WDM) function to transmit the received optical signals to an optical fiber or de-multiplexing an optical signal received from the optical fiber to transmit the de-multiplexed optical signals to the photonic IC through the inclined surface.
These limitations represent subject matter not described or reasonably suggested, in conjunction with the further limitations of the present claims, by the prior art of record.
Claims 13-14 depend from Claim 12 and therefore contain at least the same allowable subject matter.
Conclusion
The prior art cited in the attached form PTO-892 are made of record and considered pertinent to applicant's disclosure. The cited prior art describes various optical modules including integrated circuits and/or redistribution layers.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JERRY RAHLL whose telephone number is (571)272-2356. The examiner can normally be reached M-F 9:00am-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Uyen-Chau Le can be reached at 571-272-2397. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JERRY RAHLL/Primary Examiner, Art Unit 2874
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