DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/15/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 12 and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ohta (US 2021/0281775 A1).
Regarding claim 1, Ohta discloses a solid-state imaging element comprising:
a pre-stage circuit (the circuit that comprises elements 210, 211, 220 and 230 as shown in Fig. 3) that generates a pixel signal that is an analog signal a plurality of times (Figs. 3-7 and par. [0033]-[0035], [0047]-[0051] & [0064]. Note the extended mode);
a sample hold circuit (270 & 280) that holds a level of the pixel signal as a held value and updates the held value according to a level of a new pixel signal according to a determination signal predetermined (see Figs. 3-7 and par. [0054]-[0059], wherein the pixel signal held by the sample-and-hold circuit 280 is updated according to an extended mode determination signal to trigger TS to sample multiple pixel signals corresponding to E1, E2 and E3 in the time periods T1, T2 and T3 as shown in Fig. 4 and/or Fig. 6 to increase dynamic range of the image); and
a determination circuit (120/130) that determines whether or not to update the held value and supplies a signal indicating a determination result as the determination signal (Figs. 2-7 and par. [0029], [0054]-[0059]. Note that the held value is updated by sampling pixel signals multiple times when the image sensor is in the extended mode to improve dynamic range).
Regarding claims 12 and 14, the limitations of these claims are also disclosed by Ohta as discussed in claim 1.
Claims 1, 2, 12 and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lahav et al. (US 2011/0013064 A1, hereinafter “Lahav”).
Regarding claim 1, Lahav discloses a solid-state imaging element (Fig. 1) comprising:
a pre-stage circuit (110) that generates a pixel signal that is an analog signal a plurality of times (Figs. 1, 2, 14-19 and par. [0033], [0040]-[0041], [0055]-[0064]);
a sample hold circuit (encompassed by Correlated Double Sampling (CDS) circuit which is a part of readout circuit 170 shown in Fig. 1) that holds a level of the pixel signal as a held value and updates the held value according to a level of a new pixel signal according to a determination signal predetermined (Figs. 1, 2, 13-15 and par. [0037], [0040]-[0041] and [0055]-[0065], wherein the pixel signal being held is updated according a result from pixel saturation level detection so as to increase dynamic range of the pixel signal. For example, the pixel signal is updated throughout multiple time intervals T1 to T3); and
a determination circuit (160) that determines whether or not to update the held value and supplies a signal indicating a determination result as the determination signal (see par. [0037], [0055]-[0065]).
Regarding claim 2, Lahav also discloses that the determination circuit compares the pixel signal with a predetermined threshold value (predetermined saturation level) and supplies a comparison result as the determination result (see par. [0037], [0055]-[0065]).
Regarding claims 12 and 14, the limitations of these claims are also met by disclosure of Lahav as discussed in claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Lahav in view of Ikuma et al. (US 2024/0089625 A1, hereinafter “Ikuma”).
Regarding claim 8, Lahav fails to teach that the pre-stage circuit is arranged on a predetermined first chip, and the sample hold circuit is arranged on a predetermined second chip. However, this circuit arrangement is well known in the art as taught by Ikuma in Fig. 1A and paragraphs [0156]-[0157], wherein a pre-stage circuit (pixel circuit 3a) is resided in a first chip while the sample and hold circuit (10a) is resided in a second chip to reduce a number of shared elements and improve feedback effectiveness in microcells.
Therefore, it would have been obvious to one of ordinary skill in the art to combine the teaching of Lahav and Ikuma to arrive at the currently claimed features to take the advantage of the benefits taught by Ikuma above.
Regarding claim 9, it is also seen in the combination of Lahav and Ikuma that the determination circuit is arranged on the second chip (see Ikuma, Fig. 1A & 4, wherein the logic circuit is resided in the second chip).
Regarding claim 10, as shown in Fig. 1 of Lahav, the determination circuit (160) is arranged on the first chip (Lahav, par. [0033]).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Lahav in view of Kawahito (US 2009/0303358 A1).
Regarding claim 7, although Lahav teaches a digital camera which inherently comprises an analog-to-digital converter for converting the pixel signal into a digital signal (see Lahav, par. [0002]), Lahav fails to teach that the determination circuit compares the digital signal with a predetermined threshold value and supplies a comparison result as the determination result. However, a determination circuit could be implemented in either an analog domain or a digital domain as taught by Kawahito who teaches a digital determination circuit for comparing a digital signal of a pixel with a predetermined reference threshold and providing a determination result that is fed back to control pixel signal sampling and gain control (see Kawahito, Figs. 1 & 2 and par. [0045]).
Therefore, it would have been obvious to one of ordinary skill in the art to implement an alternative configuration to provide the determination circuit in a digital domain as claimed to obtain the benefit of digital signal which is less susceptible to noise than the analog counterpart, thereby improving signal integrity.
Allowable Subject Matter
Claims 3-6, 11 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 3, the prior art references of record fail to teach or suggest: “the pre-stage circuit, the sample hold circuit, and the determination circuit are arranged in each of a plurality of pixels.”
Regarding claim 4, the prior art references of record also fail to teach or suggest: “the pre-stage circuit and the sample hold circuit are arranged in each of a plurality of pixels, a pixel array section in which the plurality of pixels is arranged is divided into a predetermined number of regions, the determination circuit is arranged in each of the regions, and the pixels in the region share the determination circuit corresponding to the region.”
Regarding claim 5, the prior art references of record also fail to teach or suggest: “a logic gate that supplies a predetermined scan signal indicating a sample timing and a read timing to the sample hold circuit on a basis of the determination signal, wherein the determination circuit includes: a comparator that compares the pixel signal with a predetermined threshold value and supplies a signal indicating a comparison result as the determination signal; and a latch circuit that captures and holds the determination signal at the sample timing and initializes the determination signal at the read timing.”
Regarding claim 6, the prior art references of record also fail to teach or suggest: “a pre-stage logic gate that supplies a predetermined scan signal indicating a sample timing on a basis of the determination signal; and a post-stage logic gate that supplies a logical sum of a predetermined control signal indicating a read timing and an output signal of the pre-stage logic gate to the sample hold circuit.”
Regarding claim 11, the prior art references of record also fail to teach or suggest: “a post-stage reset transistor that initializes a level of a predetermined post-stage node, wherein the pre-stage circuit sequentially generates a predetermined reset level and a signal level corresponding to an exposure amount, the sample hold circuit includes: first and second capacitor elements; and a selection circuit that sequentially performs control to connect one of the first and second capacitor elements to the post-stage node, control to disconnect both the first and second capacitor elements from the post-stage node, and control to connect another of the first and second capacitor elements to the post-stage node, and the post-stage reset transistor initializes a level of the post-stage node when both the first and second capacitor elements are disconnected from the post-stage node.”
Regarding claim 13, the prior art references of record also fail to teach or suggest: “the pre-stage circuit and the sample hold circuit are arranged in each of a plurality of pixels, and the determination circuit determines a pixel in a region of a focused subject among the plurality of pixels as a pixel whose held value is not updated.”
Conclusion
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/NHAN T TRAN/ Primary Examiner, Art Unit 2638
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