Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-18 are presented for examination.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 17-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 17 recites “A non-transitory machine readable storage medium which stores computer software according to claim 16”. It is unclear what is meant by “according to” in this context, and the scope of the claim is therefore indefinite. For the purposes of examination, this will be interpreted to be “…which stores the computer software of claim 16”.
Claim 18 recites “A virtual machine comprising a data processor to execute a computer program comprising machine readable instructions, in which execution of the computer program causes the data processor to operate as a data processing apparatus comprising: vector processing circuitry…” A virtual machine typically connotates a software (virtual) implementation, however the claimed virtual machine includes “circuitry” which requires a hardware implementation. The scope of the claim is therefore indefinite. For the purposes of examination, this will be interpreted to be a hardware machine that supports virtualization. Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 16 is rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim does not fall within at least one of the four categories of patent eligible subject matter because claim 16 encompasses software per se. To overcome the rejection, the claim must contain a proper computer-readable storage medium that is functionally and structurally interconnected with the software. When functional descriptive material is recorded on some computer-readable storage medium, it becomes structurally and functionally interrelated to the medium and will be statutory in most cases since use of technology permits the function of the descriptive material to be realized. In re Lowry, 32 F.3d 1579, 1583-84, 32 USPQ2d 1031, 1035 (Fed. Cir. 1994).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-18 are rejected under 35 U.S.C. 103 as being unpatentable over Adelman, US Patent Application Publication 2021/0406018 (hereinafter Adelman) in view of Raikin et al., US Patent 11,321,092 (hereinafter Raikin).
Regarding claim 1, Adelman teaches:
Data processing apparatus comprising: vector processing circuitry to access an array register having at least n x n storage locations, where n is an integer greater than one (see e.g. fig. 24, para. [0059], [0187], the two-dimensional matrix tile is an array register that has n x n register storage locations), the vector processing circuitry comprising: instruction decoder circuitry to decode program instructions (see e.g. fig. 13, para. [0122]); and instruction processing circuitry to execute instructions decoded by the instruction decoder circuitry (see e.g. fig. 13, para. [0126]); in which the instruction decoder circuitry is responsive to an array access instruction, to control the instruction processing circuitry to access, for a vector of n vector elements, a set of n storage locations each having a respective array location in the array register (see e.g. fig. 24, para. [0187], n storage locations are accessed for n vector elements of destination vector).
Adelman fails to explicitly teach the array location accessed for a given vector element of the vector being defined by one or more coordinates associated with the given vector element by one or more parameters of the array access instruction.
Raikin teaches accessing an array location for a vector element using coordinates associated with the vector element by one or more parameters of an instruction (see e.g. col. 7 lines 41-67, a tensor array location is accessed based on the coordinates).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Adelman and Raikin to include the array location accessed for a given vector element of the vector being defined by one or more coordinates associated with the given vector element by one or more parameters of the array access instruction. This would have provided an advantage such as discussed by Raikin: “The tensor-access instructions manipulate elements of multi-dimensional arrays by operating directly on the multi-dimensional coordinate values of the elements (as opposed to operating on the addresses in which the elements are stored in the external memory). In this manner, the processor manipulates tensor elements by dedicated hardware, achieving higher speed than software-based solutions.” (see col. 2 lines 57-64).
Regarding claim 2, Adelman in view of Raikin teaches or suggests:
The data processing apparatus of claim 1, in which the array location accessed for the given vector element of the vector is defined by at least a pair of coordinates associated with the given vector element of the vector by parameters of the array access instruction (see e.g. Raikin col. 5 lines 18-40).
Regarding claim 3, Adelman in view of Raikin teaches or suggests:
The data processing apparatus of claim 2, in which the pair of coordinates define, for the given vector element of the vector, an array location in each of a first array direction and a second array direction different to the first array direction (see e.g. Raikin col. 5 lines 18-40).
Regarding claim 4, Adelman in view of Raikin teaches or suggests:
The data processing apparatus of claim 1, in which the array location accessed for the given vector element of the vector is defined by a coordinate in a first array direction dependent upon a vector position of the given vector element, and a coordinate in a second array direction different to the first array direction defined by a parameter of the array access instruction (see e.g. Adelman para. [0063], [0066-7], for strided accesses, the location accessed is based on the stride, which is based on the position of the current element in the access order; Raikin col. 5 lines 18-40).
Regarding claim 5, Adelman in view of Raikin teaches or suggests:
The data processing apparatus of claim 4, in which the instruction decoder circuitry is configured to select the first array direction and the second array direction from two candidate array directions in response to a parameter of the array access instruction (see e.g. Raikin col. 5 lines 18-40).
Regarding claim 6, Adelman in view of Raikin teaches or suggests:
The data processing apparatus of claim 3, in which the second array direction is orthogonal to the first array direction (see e.g. Raikin col. 5 lines 18-40).
Regarding claim 7, Adelman in view of Raikin teaches or suggests:
The data processing apparatus of claim 1, in which the array access instruction comprises an instruction selected from the list consisting of: a vector storage instruction to store data items to respective locations in the array register; and a vector retrieval instruction to retrieve data items from respective locations in the array register (see e.g. Adelman para. [0067]).
Regarding claim 8, Adelman in view of Raikin teaches or suggests:
The data processing apparatus of claim 7, in which: The data processing apparatus comprises a main memory accessible by the vector processing circuitry (see e.g. Raikin col. 7 lines 41-67).
Regarding claim 9, Adelman in view of Raikin teaches or suggests:
The data processing apparatus of claim 7, in which the array access instruction comprises an instruction selected from the list consisting of: a vector storage instruction to store vector elements of an input data vector to respective locations in the array register; and a vector retrieval instruction to retrieve data items of a set of memory locations of the main memory to respective vector elements of a destination data vector (see e.g. Adelman para. [0067], Raikin col. 7 lines 41-67).
Regarding claim 10, Adelman in view of Raikin teaches or suggests:
The data processing apparatus of claim 8, in which the vector storage instruction comprises an instruction selected from the list consisting of: a first vector retrieval instruction to retrieve vector elements of an output data vector from respective locations in the array register; and a second vector retrieval instruction to retrieve data items to a set of memory locations of the main memory from respective locations in the array register (see e.g. Adelman para. [0067], Raikin col. 7 lines 41-67).
Regarding claim 11, Adelman in view of Raikin teaches or suggests:
The data processing apparatus of claim 1, in which the instruction processing circuitry is responsive to one or more sets of predicates associated with respective vector elements to control accessing of the array register in respect of the respective vector elements (see e.g. Adelman para. [0276], [0345]).
Regarding claim 12, Adelman in view of Raikin teaches or suggests:
The data processing apparatus of claim 1, in which n depends upon a vector length applicable to the vector processing circuitry (see e.g. Adelman para. [0063], [0264], [0276], [0326]).
Regarding claim 13, Adelman in view of Raikin teaches or suggests:
The data processing apparatus of claim 12, in which the vector processing circuitry is configured to select the vector length applicable to the vector processing circuitry (see e.g. Adelman para. [0063], [0264], [0276], [0326]).
Regarding claim 14, Adelman in view of Raikin teaches or suggests:
The data processing apparatus of claim 1, comprising two or more array registers each of n x n storage locations (see e.g. Adelman para. [0057]).
Claims 15-17 are rejected for reasons corresponding to those given above for claim 1.
Claim 18 is rejected for reasons corresponding to those given above for claim 1.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN M LINDLOF whose telephone number is (571)270-1024. The examiner can normally be reached Mon-Tue 8:30-5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached at 5712703995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JOHN M LINDLOF/Primary Examiner, Art Unit 2183
Prosecution Insights