DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 16 Juley 2024 complies with the provisions of 37 CFR 1.97. Accordingly, the examiner has considered the information disclosure statement; please see attached forms PTO-1449.
Drawings
The drawings submitted have been reviewed and determined to facilitate understanding of the invention. The drawings are accepted as submitted.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 4-6 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 4 recites the limitation "the RDL" in line 6. There is insufficient antecedent basis for this limitation in the claim. For examination purposes, any redistribution layer shall be considered to anticipate the claimed “RDL.”
Claim 5 recites the limitation "the outside" in line 9 There is insufficient antecedent basis for this limitation in the claim. For examination purposes, "the outside" will be considered to refer to a structure not formed in or on the optical system-in-package or module.
Claim 6 depends from Claim 5 and is therefore indefinite for the same reasons.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 3 are rejected under 35 U.S.C. 102(a)(1) as being inherently anticipated by US Patent Application Publication US 2016/0141279 A1 to Krabe et al. (“US1”), cited in Applicant’s IDS.
Regarding Claim 1, US1 describes an optical module (see Figs 3, 5, 9) comprising:
an optical system-in-package (O-SIP) (60, 140) for generating an optical signal or receiving an optical signal, in which a photonic integrated circuit (IC) (2, 30) and an electronic IC (20) for driving or interfacing the photonic IC are molded inside a mold body (37) having a first surface and a second surface which are flat on a lower portion and an upper portion of the mold body (see Figs 3, 5, 9); and
a vertical coupler (70) mounted on an upper portion of the O-SIP and having a through hole (72, 73) corresponding to a light entrance/exit part of the photonic IC inside the mold body, wherein
an optical fiber is coupled to the through hole (inherent to the operation of the module in optical communications systems using an optical fiber, as described at [0004]).
Regarding Claim 3, US1 describes the photonic IC comprises a light emitting device (30) and a light receiving device (2; see [0052]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over US1 as applied to Claim 1 above.
Regarding Claim 4, US1 describes:
first and second metal structures (133) for heat dissipation having respective upper surfaces bonded to lower portions of the photonic IC and the electronic IC and respective lower surfaces exposed (see [0067], Fig 5);
a third structure (10) for a via that is inserted through the mold body between the photonic IC and the electronic IC, and has an upper end connected to a redistribution layer (“RDL”) (121a) and a lower end exposed (see Figs 3, 5, 9); and
a metal connection layer (42) that connects the RDL to the lower portions of the photonic IC and the electronic IC and has a lower surface of the metal connection layer exposed by interconnecting the lower surfaces of the first to third metal structures (see Figs 3, 5, 9).
US1 does not describe the third structure as a metal structure. US1 describes the third structure as formed from, “bulk material having a known electrical conductivity,” ([0043]) and having, “an electrical conductivity that is sufficiently high to allow it to be used as an electrical pathway” ([0053]). US1 is silent as to the particular material of the third structure. Metal materials are well-known in the art as materials having a known electrical conductivity that is sufficiently high to allow it to be used as an electrical pathway. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to form the third structure of US1 from a metal, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Regarding Claim 5, US1 describes the O-SIP comprising:
the mold body having a first surface and a second surface which are flat on a lower portion and an upper portion of the mold body, respectively (see Figs 3, 5, 9);
the photonic integrated circuit (IC) molded inside the mold body (see Figs 3, 5, 9) to expose a bonding pad (3, 32) on the first surface;
the electronic IC molded to be spaced apart from the photonic IC inside the mold body (see Figs 3, 5, 9) to expose the bonding pad (22) on the first surface; and
a RDL (121a) formed on the second surface of the mold body and having a plurality of terminals interconnecting the photonic IC and the electronic IC (see Figs 3, 5, 9).
US1 does not describe the plurality of terminal pads as a plurality of fan-out terminal pads electrically connected to the outside. However, it is well-known in the art for form a RDL having a plurality of fan-out terminal pads electrically connected to an area outside the module for providing connections to external components including power sources and controllers. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to form the RDL of US1 having a plurality of fan-out terminal pads electrically connected to the outside. The motivation for doing so would have been to allow for electrical connection to external components.
Regarding Claim 6, US1 describes the RDL arranged on an upper portion of the light entrance/exit part of the photonic IC has an opening (see Figs 3, 5, 9).
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over US1 in view of US Patent Application US 2007/0267569 A1 to Ueno et al. (“US2”).
Regarding Claim 7, US1 describes an optical module (see Figs 3, 5, 9) comprising:
an optical system-in-package (O-SIP) (60, 140) for generating an optical signal or receiving an optical signal, in which a photonic integrated circuit (IC) (2, 30) and an electronic IC (20) for driving or interfacing the photonic IC are molded inside a mold body (37) having a first surface and a second surface which are flat on a lower portion and an upper portion of the mold body (see Figs 3, 5, 9); and
a vertical coupler (70) having a lower surface mounted on an upper portion of the O-SIP (via 61).
US1 does not describe an optical fiber holder or the vertical coupler having an accommodation space.
US2 describes an optical module (see Fig 6) comprising:
An optical package (2, 21, 12, 111) for generating an optical signal or receiving an optical signal (see [0025]);
an optical fiber holder (3B) coupled to rear end portions of a plurality of optical fibers (4) to support at least one optical fiber therein and having a pair of coupling recesses (3a); and
a vertical coupler (13B) having a lower surface mounted on an upper portion of optical package, having an accommodation space (132) for accommodating the optical fiber holder at an upper end thereof, and having a pair of coupling protrusions (15) protruding from both sides thereof to be coupled to the pair of coupling recesses.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to use the fiber holder and coupler structures of US2 in the module of US1 to allow for connection to optical fibers to the module. The motivation for doing so would have been to allow for the use of the module in optical communications, as described by US1 at [0004]).
Regarding Claim 8, US2 describes the optical fiber holder coupled to the accommodation space of the vertical coupler, the at least one optical fiber optically aligned with light entrance/exit part of a light emitting device (12) or a light receiving device (12; see [0071], [0075]).
Claims 9 is rejected under 35 U.S.C. 103 as being unpatentable over US1 in view of US Patent Application US 2017/0363825 A1 to Sataki (“US3”), cited in Applicant’s IDS.
Regarding Claim 9, US1 describes an optical module comprising (see Figs 3, 5, 9):
an optical system-in-package (O-SIP) (60, 140) for generating an optical signal or receiving an optical signal, in which a photonic integrated circuit (IC) (2, 30) and an electronic IC (20) for driving or interfacing the photonic IC are molded inside a mold body (37) having a first surface and a second surface which are flat on a lower portion and an upper portion of the mold body; and
a first printed circuit board (PCB) (70) having the O-SIP mounted on the lower surface thereof (see Figs 3, 9), and a through hole (72, 73) forming an optical path when an optical signal is generated in a vertical direction or an optical signal is received from the photonic IC at a portion corresponding to a light entrance/exit part of the photonic IC;
US1 does not describe an optical fiber holder.
US3 describes an optical module (see Fig 14) comprising:
an optical package (40, 45) for generating an optical signal or receiving an optical signal;
a first printed circuit board (PCB) (20) having the package mounted on the lower surface thereof, and a through hole (21a, 21b) forming an optical path when an optical signal is generated in a vertical direction or an optical signal is received from the optical package at a portion corresponding to a light entrance/exit part of the optical package; and
an optical fiber holder (10) coupled to rear end portions of a plurality of optical fibers (30) so as to support the plurality of optical fibers therein, and having a front end portion on which the package is mounted through the through hole (see Figs 14).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to use the fiber holder and coupler structures of US2 in the module of US1 to allow for connection to optical fibers to the module. The motivation for doing so would have been to allow for the use of the module in optical communications, as described by US1 at [0004]).
Claims 10 is rejected under 35 U.S.C. 103 as being unpatentable over US1 and US3, as applied to Claim 9, in view of US Patent Application US 2003/0053767 A1 to Cheng et al. (“US4”).
Regarding Claim 10, US3 describes the first PCB as a flexible PCB (see [0031]).
US1 and US3 are both silent as to any further components connected to the PCB.
US4 describes an optical module (see Figs 1, 2, 6, 8, and 10) comprising:
an optical package (52) for generating an optical signal or receiving an optical signal, in which a photonic integrated circuit (IC) (40) and an electronic IC (86) for driving or interfacing the photonic IC; a first printed circuit board (PCB) (60) having the optical package mounted on the lower surface thereof; and
an optical fiber holder (12) coupled to rear end portions of a plurality of optical fibers (17) so as to support the plurality of optical fibers therein, and having a front end portion on which the optical package is mounted (see Fig 8), wherein,
the first PCB is a flexible PCB (see [0029]), and
further comprising a second PCB (18) on which a plurality of electronic components (22, 110) are mounted to perform transmission/reception control optical package, and to which one end of the first PCB is connected (see Figs 2, 6, 8, 10).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to use the module of US1 and US3 with the additional PCB and electronic component structures of US4. The motivation for doing so would have been to allow for integration of the optical module into a larger communications system using a jack structure (see US4 at [0029]).
Allowable Subject Matter
Claim 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 2 describes the O-SIP comprising a transmitter optical sub-assembly (TOSA) to which a light emitting device is applied as the photonic IC and a receiver optical sub-assembly (ROSA) to which a light receiving device is applied as the photonic IC.
These limitations represent subject matter not described or reasonably suggested, in conjunction with the further limitations of the present claims, by the prior art of record.
Conclusion
The prior art cited in the attached form PTO-892 are made of record and considered pertinent to applicant's disclosure. The cited prior art describes various optical modules with optical packages and/or PCBs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JERRY RAHLL whose telephone number is (571)272-2356. The examiner can normally be reached M-F 9:00am-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Uyen-Chau Le can be reached at 571-272-2397. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JERRY RAHLL/Primary Examiner, Art Unit 2874
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