DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note by the Examiner
For clarity, references to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and examiner explanations for 102 &/or 103 rejections are provided in parenthesis.
Claim Objections
Claim objected to because of the following informalities:
In the twenty-third line of claim 1, the comma between "second region" and "and" should be a semicolon in order to improve grammatical clarity. In the twenty-fifth line of claim 1, "the" before "order of" should be "an" due to lack of antecedent basis. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kato et al. (Pub. No.: US 20210280550 A1), hereinafter as Kato.
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Image A: close up of Kato Fig. 1, showcasing first, second, and connection regions.
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Image B: annotation of Kato Fig. 1, showcasing order of wiring boards.
With regards to claim 1, Kato teaches a semiconductor device (see Kato Fig. 1, semiconductor module 1; Kato [0020]) provided in an inverter (see Kato [0020] “The semiconductor device according to this embodiment is applied to a power conversion device in a power module, for example, and is a power module included in an inverter circuit.”), the semiconductor device comprising: a positive electrode wiring board (see Kato Fig. 1, first conductive layer 23 and second conductive layer 24; Kato [0028]) provided with a positive electrode terminal (see Kato Fig. 1, positive electrode terminal 16; Kato [0024]); a negative electrode wiring board (see Kato Fig. 1, fifth conductive layer 27 and sixth conductive layer 28; Kato [0028]) provided with a negative electrode terminal (see Kato Fig. 1, negative electrode terminal 17; Kato [0024]); and an alternating-current wiring board (see Kato Fig. 1, third conductive layer 25 and fourth conductive layer 26; Kato [0028]) provided with an alternating-current terminal (see Kato Fig. 1, output terminal 15; Kato [0024]), on an insulation layer (see Kato Fig. 2, insulating plate 20; Kato [0025]) of a substrate (see Kato Fig. 2, base plate 10; Kato [0021]) included in the semiconductor device (see Kato Fig. 2), wherein the positive electrode wiring board has a plurality of upper arm semiconductor elements (see Kato Fig. 1, first semiconductor elements 3a and second semiconductor elements 3b; Kato [0036]) electrically connected in parallel (see Kato [0037]: “The two first semiconductor elements 3a are disposed at positions deviated to the Y-direction positive side of the first conductive layer 23 and are connected in parallel.”; and see Kato [0038]: “The two second semiconductor elements 3b are disposed at positions deviated to the Y-direction positive side of the second conductive layer 24 and are connected in parallel.”), the alternating-current wiring board has a plurality of lower arm semiconductor elements (see Kato Fig. 1, third semiconductor elements 3c and fourth semiconductor elements 3d; Kato [0036]) electrically connected in parallel (see Kato [0039]: “The two third semiconductor elements 3c are disposed at positions deviated to the Y-direction negative side of the third conductive layer 25 and are connected in parallel.”; and see Kato [0040]: “The two fourth semiconductor elements 3d are disposed at positions deviated to the Y-direction negative side of the fourth conductive layer 26 and are connected in parallel.”), the plurality of upper arm semiconductor elements and the alternating-current wiring board being electrically connected to each other (see Kato Fig. 1) by first wiring members (see Kato Fig. 1, first wire 4a and second wire 4b; Kato [0043]), respectively, and the plurality of lower arm semiconductor elements and the negative electrode wiring board being electrically connected to each other (see Kato Fig. 1) by second wiring members (see Kato Fig. 1, third wire 4c and fourth wire 4d; Kato [0043]), respectively, the alternating-current wiring board has a first region (see Image A) to which the first wiring members are connected (see Image A), a second region (see Image A) in which the plurality of lower arm semiconductor elements are provided (see Image A), and a connection region (see Image A) that connects the first region and the second region (see Image A), the connection region being provided at a position (see Image A) opposite to the positive electrode terminal (see Image A) and the negative electrode terminal with a region in between where the first wiring member connects the positive electrode wiring board and the first region (see Kato Fig. 1 and Image A, where the wiring members are located between the connection region and the positive and negative terminals.) and a region in between where the second wiring member connects the negative electrode wiring board and the second region (see Kato Fig. 1 and Image A, where the wiring members are located between the connection region and the positive and negative terminals.), and the positive electrode wiring board, the negative electrode wiring board, the first region, and the second region are arranged on the insulation layer (see Kato Fig. 1 and Fig. 2) in an order of the positive electrode wiring board, the negative electrode wiring board, the first region, and the second region (see Image B).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Kato, in view of Pahn et al. (Pub. No.: US 20220311349 A1), hereinafter as Pahn.
With regards to claim 4, Kato teaches the semiconductor devices according to claim 1 (see Kato Figs. 1&2).
Kato does not teach an Inverter comprising the semiconductor devices according to claim 1, wherein the semiconductor devices are arranged side by side in parallel with a short-dimension direction of the semiconductor device, and are connected to a direct-current voltage input terminal via a smoothing capacitor element.
Pahn teaches an Inverter (see Pahn Fig. 2, inverter 100; Pahn [0044]) comprising semiconductor devices (see Pahn Fig. 2, half-bridge 12A, 12B, 12C; and see Pahn [0046]: “The inverter 100 comprises a power module 10 (see FIG. 2), which comprises a plurality of (in this case by way of example three) half-bridges 12A, 12B, 12C. Each half-bridge 12A, 12B, 12C comprises a substrate (not shown), on which a plurality of semiconductor switching elements (not shown) are mounted.”), wherein the semiconductor devices are arranged side by side in parallel (see Pahn Fig. 2, and see Pahn [0004]: “The high side and the low side may each comprise one or a plurality of individual switches/semiconductor switching elements that are connected in parallel.”) with a short-dimension direction (along the horizontal direction of Pahn Fig. 2) of the semiconductor device (see Pahn Fig. 2), and are connected to a direct-current voltage input terminal (see Pahn Fig.2, first DC busbar 24 and second DC busbar 26; and see Pahn [0048]: “Furthermore, the first DC busbar 24 and the second DC busbar 26 are connected to the direct current source (not shown) via the intermediate circuit capacitor 23. In this way, the half-bridges 12A, 12B, 12C can be supplied with direct currents from the current source.”) via a smoothing capacitor element (see Pahn Fig. 2, intermediate circuit capacitor 23; and see Pahn [0005]: “The intermediate circuit capacitor is used to smooth the DC-side input voltage in order to reduce voltage jumps.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor device of Kato with the inverter taught by Pahn, by substituting the undefined semiconductor devices in Pahn with that of Kato, in order to reduce voltage jumps and protect the semiconductor device of Kato (see Pahn [0005]: “The intermediate circuit capacitor is used to smooth the DC-side input voltage in order to reduce voltage jumps.”).
Allowable Subject Matter
Claims 2 and 3 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 2, the prior art does not teach or render obvious that the first wiring members and the second wiring members are alternately arranged.
Regarding claim 3, the prior art does not teach or render obvious that the first wiring member is longer as the first wiring member is closer to the connection region, and the second wiring member is longer as the second wiring member is closer to the negative electrode terminal.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure:
Okayama (US 20150155797 A1)
Iwahashi et al. (US 20190035771 A1)
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/E.T.B./Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
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