DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Foreign priority is not claimed for this application.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 10/14/2024, 12/04/2024, 02/25/2025, 06/24/2025, 09/29/2025, 10/31/2025, 01/31/2026, and 05/11/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-11, 13, and 16-17is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by US 20140266432 by Scott et al.
Regarding claim 1, Scott teaches a transmission chain comprising:
a power amplifier stage (Fig. 8 #202);
a detection and alignment circuit (#204) coupled to the power amplifier stage and configured to detect a phase of a signal associated with the power amplifier stage (Par. 115-119); and
an amplitude modulation (AM)-to-phase modulation (PM) (AM-PM) predistortion circuit (#208, 212) coupled to the detection and alignment circuit (#204) and the power amplifier stage (#202), the AM-PM predistortion circuit configured to provide a phase correction signal to the signal based on detected characteristics from the detection and alignment circuit (Par. 121-122), where the phase correction signal operates orthogonally to any AM-AM predistortion circuit (Fig. 8 unless otherwise stated, #204 is correcting the AM part while #212 is independently correcting the phase part, so they are ideally orthogonal to each other).
Regarding claim 2, Scott teaches the transmission chain of claim 1, wherein the power amplifier stage comprises:
an input (Fig. 9 input into #222);
a driver stage coupled to the input (Par. 60;
an output stage coupled to the driver stage with a node therebetween (Fig. 9 nodes in between the different stages); and
an output coupled to the output stage (output of #264).
Regarding claim 3, Scott teaches the transmission chain of claim 2, wherein the detection and alignment circuit (Fig. 9 #224) is coupled to the input (#224 is coupled to the node at the input of #260 through #226 and #232).
Regarding claim 4, Scott teaches the transmission chain of claim 2, wherein the detection and alignment circuit is coupled to the output (Fig. 9 #224 coupled to output of #264 through #26 and #244).
Regarding claim 5, Scott teaches the transmission chain of claim 2, wherein the detection and alignment circuit is coupled to the node between the driver stage and the output stage (Fig. 9 #224 is coupled to one of the many nodes in between the stages through #226 and #236 or #240).
Regarding claim 6, Scott teaches the transmission chain of claim 2, further comprising a second detection and alignment circuit coupled to the node between the driver stage and the output stage (Fig. 9 #224 has multiple sensors/detectors and one can be coupled to the node between the different stages).
Regarding claim 7, Scott teaches the transmission chain of claim 6, further comprising a second AM- PM predistortion circuit coupled to the second detection and alignment circuit (Fig. 9 shows multiple predistortion circuits #232-#244 coupled to #224).
Regarding claim 8, Scott teaches the transmission chain of claim 2, wherein the AM-PM predistortion circuit is coupled to the input and the phase correction signal is applied at the input (Fig. 9 #224 coupled to input of #260 and phase correction signal #246 is applied at input).
Regarding claim 9, Scott teaches the transmission chain of claim 2, wherein the AM-PM predistortion circuit is coupled to the output and the phase correction signal is applied at the output (Fig. 9 #224 is coupled to the output of #264 and phase correction signal #258 is applied at the output).
Regarding claim 10, Scott teaches the transmission chain of claim 2, wherein the AM-PM predistortion circuit is coupled to the node and the phase correction signal is applied at the node (Fig. 9 #224 is coupled to the nodes in between the stages and phase correction signal #250/254 is applied at the node(s)).
Regarding claim 11, Scott teaches the transmission chain of claim 1, further comprising a digital controller coupled to the AM-PM predistortion circuit and configured to control the AM- PM predistortion circuit (Fig. 8 #208).
Regarding claim 12, Scott teaches the transmission chain of claim 11, wherein the digital controller is configured to set a quiescent point in the AM-PM predistortion circuit (Fig. 8, 13; Par. 142; the voltage of the input will vary with the drive level and in order for the varactor to cover a range of AM-PM phase control, it is essential that it is DC biased at a quiescent point (the DC voltage is set from the control circuit)).
Regarding claim 13, Scott teaches the transmission chain of claim 1, wherein the AM-PM predistortion circuit comprises a varactor (Par. 121).
Regarding claim 15, Scott teaches the transmission chain of claim 1, wherein the AM-PM predistortion circuit is configured to provide a phase advance correction signal in a first mode and a phase delay correction signal in a second mode (Fig. 13; The quiescent point is set somewhere in the middle. When the capacitance increases it will cause phase advance and when the capacitance decreases will cause phase delay).
Regarding claim 16, Scott teaches the transmission chain of claim 1, wherein the power amplifier stage is single ended (Fig. 8).
Regarding claim 17, Scott teaches the transmission chain of claim 1, wherein the power amplifier stage is differential (Par. 47).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20140266432 by Scott et al.
Regarding claim 14, Scott teaches the transmission chain of claim 1, and while a plurality of varactors with switches are not shown, it is well known in the art that a person of ordinary skill can implement phase correction using these elements, as taught in Col. 5 lines 11-16 and Col. 6 lines 5-20 of US 9503040 by Mosinskis et al.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NAREH SHAMIRYAN whose telephone number is (703)756-4616. The examiner can normally be reached M-F: 7:00AM-4:00PM PT.
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/NAREH SHAMIRYAN/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843
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