DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Foreign priority is not claimed for this application.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 14 October 2024; 04 December 2024; 25 February 2025; 24 June 2025; 29 September 2025; 29 September 2025; 31 October 2025; 31 January 2026; 11 May 2026; and 20 August 2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, examiner is unsure how this is considered an open loop. It’s a closed loop, and the correction is not “real time adaptive,” but rather based on a predetermined LUT. Although it’s done following a LUT, it’s a closed loop because it’s looping back to the input. Due to this the claim is unclear and indefinite. Appropriate correction is required. Claims 2-18 inherit this rejection.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 7, 10-13, and 17 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by US 20050017801 by Bachman, II et al.
Regarding claim 1, Bachman teaches a transmission chain (Fig. 3) comprising:
a power amplifier stage (10);
a bias circuit coupled to the power amplifier stage (74; par. 41 power supply sets the bias of the amplifier);
a detection and alignment circuit coupled to the power amplifier stage and configured to detect a power level of a signal associated with the power amplifier stage (38 is sampling the output signal in RF and the down converter is detecting the envelope); and
an amplitude modulation (AM)-to-amplitude modulation (AM) (AM-AM) predistortion circuit (blocks 64-66-52-72-74) coupled to the detection and alignment circuit and the bias circuit, the AM-AM predistortion circuit configured to provide a correction signal to the bias circuit based on detected characteristics from the detection and alignment circuit thereby forming an open loop feedback circuit that minimizes delay between measuring distortion and correction (Abstract; Par. 36; Envelope detector and comparison through LUT is correcting AM-AM).
Regarding claim 7, Bachman teaches the transmission chain of claim 1, further comprising a digital control circuit (processor 52) coupled to the AM-AM predistortion circuit and configured to control the AM-AM predistortion circuit based on one or more of a frequency, power mode, temperature, and cellular mode.
Regarding claim 10, Bachman teaches the transmission chain of claim 1, further comprising a digital controller coupled to the AM-AM predistortion circuit and configured to control the AM- AM predistortion circuit (processor 52).
Regarding claim 11, Bachman teaches the transmission chain of claim 1, further comprising a digital controller coupled to the bias circuit (74) and configured to control the bias circuit (the processor 52 sends control signals to everything in the system).
Regarding claim 12, Bachman teaches the transmission chain of claim 11, wherein the digital controller comprises a look-up table (LUT) (processor 52 coupled to LUT 14’’).
Regarding claim 13, Bachman teaches the transmission chain of claim 12, wherein the digital controller comprises at least one digital-to-analog converter (DAC) (Fig. 2 shows DACs in the predistorter circuit. Amplifier circuits consist of ADCs and DACs because an amplifier doesn’t understand digital signals. The digital controller will naturally consist of at least one DAC in order to properly communicate with the amplifier).
Regarding claim 17, Bachman teaches the transmission chain of claim 1, wherein the power amplifier stage (10) is single ended.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-4, 14-16, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20050017801 by Bachman, II et al.
Regarding claim 2, Bachman teaches the transmission chain of claim 1, wherein the power amplifier stage comprises:
an input (input into 10);
an output coupled to the output stage (RF OPT).
Bachman is silent on the power amplifier comprising a driver and output stage with a node therebetween, however, this is very well known in power amplifier configurations that are used for more gain. Paragraph 80 of US 20140266432 by Scott et al. teaches that a RF amplification circuit can be divided into driver and final (output) stages.
Regarding claim 3, Bachman teaches the transmission chain of claim 2, wherein the detection and alignment circuit is coupled to the input (Abstract; the circuit includes an input loop with predistortion values that are applied to the input signal based on the detected power in the input signal).
Regarding claim 4, Bachman teaches the transmission chain of claim 2, wherein the detection and alignment circuit (38) is coupled to the output.
Regarding claim 14, Bachman teaches the transmission chain of claim 1, and while it’s silent on the specific structure of the bias circuit, bias circuits having at least one current mirror are simply a design choice that’s known to those skilled in the art, as taught, for example, in Col. 3 lines 1-4 of US 12015382 by Haji Mokhtar et al.
Regarding claim 15, Bachman teaches the transmission chain of claim 1, and while it doesn’t specify expansion or compression of an output signal due to the correction signal, it is well known in the art that the bias signal causes AM-AM response to either expand or compress based on the bias level. If it’s biased in high class A, then it compresses. If it’s biased in low class AB or class C, it expands.
Regarding claim 16, Bachman teaches the transmission chain of claim 1, and while it doesn’t specify expansion or compression of an output signal due to the correction signal, it is well known in the art that the bias signal causes AM-AM response to either expand or compress based on the bias level. If it’s biased in high class A, then it compresses. If it’s biased in low class AB or class C, it expands.
Regarding claim 18, Bachman teaches the transmission chain of claim 1, and while it doesn’t mention a differential power amplifier stage, single and differential inputs are well known in the art of amplifiers as taught in par. 47 of US 20140266432 by Scott et al.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bachman as applied to claims 1-2 above, and further in view of US 20140266432 by Scott et al.
Regarding claim 5, Bachman teaches the transmission chain of claim 2, but fails to teach that the detection and alignment circuit is coupled to the node between the driver stage and the output stage.
However, Scott teaches an analog predistortion amplifier circuit with a detection and alignment circuit (Fig. 9 224) that is coupled to a node between a driver stage and a subsequent stage (Fig. 9). It would be obvious to a person of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Scott with the circuit of Bachman because it is generally advantageous to correct a non-linearity as locally as possible (Scott Par. 130)
Allowable Subject Matter
Claim 6 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The prior art fails to teach a second bias circuit, a second detection and alignment circuit, and a second AM-AM predistortion circuit.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NAREH SHAMIRYAN whose telephone number is (703)756-4616. The examiner can normally be reached M-F: 7:00AM-4:00PM PT.
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/NAREH SHAMIRYAN/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843
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