Prosecution Insights
Last updated: April 19, 2026
Application No. 18/730,510

Electronic Circuit Arrangement for Current Limitation

Non-Final OA §102§112
Filed
Jul 19, 2024
Examiner
SREEVATSA, SREEYA
Art Unit
2838
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Siemens Aktiengesellschaft
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
2y 9m
To Grant
88%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allow Rate
219 granted / 255 resolved
+17.9% vs TC avg
Minimal +2% lift
Without
With
+2.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
39 currently pending
Career history
294
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
47.6%
+7.6% vs TC avg
§102
35.3%
-4.7% vs TC avg
§112
14.5%
-25.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 255 resolved cases

Office Action

§102 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claims 5-10 are pending in this application. Claims 1-4 are cancelled. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) was submitted on 07/19/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Drawings The drawings are objected to because, Fig. 1 “USb” should be –USh--. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the A controller stage of claim 5, A load of claim 5, An output of the controller stage of claim 5, Switching contact of claim 5, must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Specification The disclosure is objected to because of the following informalities: Page 9 recites “a controller stage (RS)”. RS is not shown in FIG 1. Appropriate correction is required. Claim Objections Claim 5 objected to because of the following informalities: Claim 5 line 5, “said power semiconductor” should be –the power semiconductor--. Similar corrections are required in several instance of claim 1, where “said” should be replaced with –the--. Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 5-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 5 line 3 recites “a controller stage”. Specification page 9 refers to controller stage as RS in fig.1. RS is not shown in fig.1. Specification does not provide further clarification on the components of controller stage. It is unclear which components in fig.1 comprises controller stage. For the purposes of examination, controller stage is interpreted to be stage comprising R4. Claim 5 line 6 recites “a switching contact of a circuit breaker”. Circuit breaker is identified as BJT Q1 in specification. A BJT conventionally does not have switching contacts, unlike conventional circuit breaker with contacts and movable arms. It is unclear what is considered as switching contacts. For the purposes of examination, the collector and emitter of Q1 is interpreted to be the switching contacts. Claims 6-10 are rejected for the same reasons as stated above for claim 5. Claim 7 lines 2-3 recites “the control input”. It is unclear if it is referring to power semiconductor, circuit breaker or semiconductor switch. For the purpose of examination, the above limitation is interpreted to apply to power semiconductor. Claims 8-10 are rejected for the same reasons as stated above for claim 7. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 5-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kraithorn (JP H02226808 A). Regarding claim 5, Kraithorn teaches an electronic circuit arrangement for current limitation in a load circuit (abstract, securely display the overcurrent protecting function), comprising: a controller stage (e.g. stage comprising G, fig.12); a power semiconductor (i.e. MOS transistor M1, fig.12) arranged between a supply voltage (i.e. supply voltage VB and ground, fig.12) and a load (i.e. load RL, fig.12), a control input of the power semiconductor (e.g. gate of M1, fig.12) being connected to an output of the controller stage (e.g. output of G, fig.12) and a switching contact (e.g. collector and emitter of T1, fig.12) of a circuit breaker (i.e. bipolar transistor T1, fig.12); a shunt resistor (i.e. current sensing resistor Rs, fig.12) inserted into the load (e.g. Rs is connected to RL via VDS, fig.12), a voltage occurring in the shunt resistor increasing a voltage potential at a control input of the circuit breaker (it is necessarily true that voltage increase across Rs will increase voltage at the base of T1, fig.12); and a current source (e.g. current mirror MOS transistor M2, fig.12) connected to the control input of the circuit breaker (e.g. M2 is connected to base of T1, fig.12), the current source generating a bias voltage at the control input of the circuit breaker (page 3, Current i which flows through current mirror MOS transistor M2 … in order to turn on bipolar transistor T1) via a series resistor (page 3, current sensing resistor Rs which consists of diffused resistors); wherein the current source has a negative temperature coefficient (page 3, resistance of a current sensing resistor decreases by the rise of ambient temperature). Regarding claim 6, Kraithorn teaches the electronic circuit arrangement as claimed in claim 5, wherein the power semiconductor comprises a metal oxide semiconductor field effect transistor (page 1, main MOS transistor M1). Regarding claim 7, Kraithorn teaches the electronic circuit arrangement as claimed in claim 5, wherein the current source comprises a semiconductor switch (i.e. current mirror MOS transistor M2, fig.12) having a potential which is established at the control input via a temperature-dependent voltage divider (page 3, the resistance of a current sensing resistor decreases by the rise of ambient temperature) (e.g. divider comprising M2, Ri and Rs, fig.12). Regarding claim 8, it is rejected for the same reasons as stated above for claim 7. Regarding claim 9, Kraithorn teaches the electronic circuit arrangement as claimed in claim 5, wherein the current source comprises a semiconductor switch (i.e. current mirror MOS transistor M2, fig.12) having a voltage potential which is formed at the control input in a temperature-dependent manner via a voltage divider (page 3, the resistance of a current sensing resistor decreases by the rise of ambient temperature) (e.g. divider comprising M2, Ri and Rs, fig.12) formed from diodes (e.g. MOSFET M2 has intrinsic diodes, fig.12) and resistors (e.g. resistors Ri and Rs, fig.12). Regarding claim 10, it is rejected for the same reasons as stated above for claim 9. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SREEYA SREEVATSA whose telephone number is (571)272-8304. The examiner can normally be reached M-F 8am-5pm ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V Tran can be reached at (571) 270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SREEYA SREEVATSA/Primary Examiner, Art Unit 2838 02/28/2026
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Prosecution Timeline

Jul 19, 2024
Application Filed
Feb 28, 2026
Non-Final Rejection — §102, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
88%
With Interview (+2.5%)
2y 9m
Median Time to Grant
Low
PTA Risk
Based on 255 resolved cases by this examiner. Grant probability derived from career allow rate.

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