DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 5-10 are pending in this application. Claims 5, 7-8 and 10 have been amended.
Response to Arguments
Applicant's arguments filed 07/30/2026 have been fully considered but they are not persuasive.
On page 7 of Remarks filed 07/30/2026, applicant argues
This "current source" (M2) is not an independent current source generating a bias voltage as expressly recited in independent claim 5, i.e., "a current source connected to the control input of the protective transistor, said current source generating a bias voltage at the control input of the protective transistor via a series resistor".
Examiner disagrees respectfully. Claim 5 does not recite or imply “independent current source”. Although it can be seen in fig.1 of instant application that the voltage source for Q11 is HV and voltage source for M1 is V+, no such distinction is made in the claims. Prior art Kraithorn (JP H02226808 A) fig.12 does indicate that a current i flows through M2 (irrespective of M2 being a current mirror), which will affect the voltage VBE. Transistor M2 is the broadest reasonable interpretation of the “current source” of claim 5.
On page 7 of Remarks filed 07/30/2026, applicant argues
Under the proffered analysis, the resister Rs corresponds to both the "shunt resistor" and the "series resistor" of independent claim 5. However, within independent claim 5 these are two distinct components (R1 and R2), each with different functions.
On page 3 of prior art Kraithorn, it recites “current sensing resistor Rs which consists of diffused resistors”. Examiner interprets this as multiple resistors. A few of these multiple resistors Rs are interpreted as claim equivalent of “shunt resistor” and other few are interpreted as claim equivalent of “series resistor”. Additionally, any wiring connecting transistor M2 of fig.12 will also have inherent resistance.
On page 7 of Remarks filed 07/30/2026, applicant argues
Moreover, the "negative temperature coefficient" of applicant's claims is a deliberate design feature of the current source Q11.
Prior art Kraithorn fig.12 Rs is understood to be a purposeful design. In view of broadest reasonable interpretation, Rs is considered as having claim equivalence of "negative temperature coefficient".
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 5-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kraithorn (JP H02226808 A).
Regarding claim 5, Kraithorn teaches an electronic circuit arrangement for current limitation in a load circuit (abstract, securely display the overcurrent protecting function), comprising:
a controller stage (e.g. stage comprising G, fig.12);
a power semiconductor (i.e. MOS transistor M1, fig.12) arranged between a supply voltage (i.e. supply voltage VB and ground, fig.12) and a load (i.e. load RL, fig.12), a control input of the power semiconductor (e.g. gate of M1, fig.12) being connected to an output of the controller stage (e.g. output of G, fig.12) and a switching path (e.g. collector and emitter of T1, fig.12) of a protective transistor (i.e. bipolar transistor T1, fig.12);
a shunt resistor (i.e. current sensing resistor Rs, fig.12) inserted into the load (e.g. Rs is connected to RL via VDS, fig.12), a voltage occurring in the shunt resistor increasing a voltage potential at a control input of the protective transistor (it is necessarily true that voltage increase across Rs will increase voltage at the base of T1, fig.12); and
a current source (e.g. current mirror MOS transistor M2, fig.12) connected to the control input of the protective transistor (e.g. M2 is connected to base of T1, fig.12), the current source generating a bias voltage at the control input of the protective transistor (page 3, Current i which flows through current mirror MOS transistor M2 … in order to turn on bipolar transistor T1) via a series resistor (page 3, current sensing resistor Rs which consists of diffused resistors) (some of the multiple Rs is interpreted as shunt resistor and some are interpreted as series resistor);
wherein the current source has a negative temperature coefficient (page 3, resistance of a current sensing resistor decreases by the rise of ambient temperature).
Regarding claim 6, Kraithorn teaches the electronic circuit arrangement as claimed in claim 5, wherein the power semiconductor comprises a metal oxide semiconductor field effect transistor (page 1, main MOS transistor M1).
Regarding claim 7, Kraithorn teaches the electronic circuit arrangement as claimed in claim 5, wherein the current source comprises a semiconductor switch (i.e. current mirror MOS transistor M2, fig.12) having a potential which is established at the control input of the protective transistor via a temperature-dependent voltage divider (page 3, the resistance of a current sensing resistor decreases by the rise of ambient temperature) (e.g. divider comprising M2, Ri and Rs, fig.12).
Regarding claim 8, it is rejected for the same reasons as stated above for claim 7.
Regarding claim 9, Kraithorn teaches the electronic circuit arrangement as claimed in claim 5, wherein the current source comprises a semiconductor switch (i.e. current mirror MOS transistor M2, fig.12) having a voltage potential which is formed at the control input in a temperature-dependent manner via a voltage divider (page 3, the resistance of a current sensing resistor decreases by the rise of ambient temperature) (e.g. divider comprising M2, Ri and Rs, fig.12) formed from diodes (e.g. MOSFET M2 has intrinsic diodes, fig.12) and resistors (e.g. resistors Ri and Rs, fig.12).
Regarding claim 10, it is rejected for the same reasons as stated above for claim 9.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SREEYA SREEVATSA whose telephone number is (571)272-8304. The examiner can normally be reached M-F 8am-5pm ET.
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/SREEYA SREEVATSA/Primary Examiner, Art Unit 2838 08/27/2026
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