DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) filed on July 19th, 2024, May 16th, 2025, and August 7th, 2026 are being considered by the examiner.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. However, should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e). Failure to provide a certified translation may result in no benefit being accorded for the non-English application.
Claim Objections
Claim 8 is objected to for the following reasons. Claim 8 refers to “a first layer”, but the specification does not define “a first layer”. Rather, the specification appears to refer to “III-nitride-based DSL” in place of “a first layer”. Pursuant to MPEP 2173.03 and 37 CFR 1.75(d)(1), correspondence between specification and claims is required. Appropriate correction is deemed to be required to correct the correspondence issue. For the purposes of compact prosecution and a complete record, Examiner shall interpret “a first layer” as being equivalent to “III-nitride based DSL layer” as defined in the specification.
Claims 9, 12, 13 are objected to for the following reasons. Claims 9, 12, 13 refers to “buffer layer”, but the initial recitation of the element is "III-nitride-based buffer layer". Appropriate correction is deemed to be required to correct the correspondence issue. For the purposes of compact prosecution and a complete record, Examiner shall interpret “buffer layer” as being equivalent to “III-nitride-based buffer layer” recited in Claim 1.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
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Annotated Fig.12 – Wang
Claim(s) 1 and 29-31 is/are rejected under 35 U.S.C 102(a)(1) as being anticipated over Shumin Wang (US 20150024223 A1), hereinafter Wang.
As to Claim 1, Wang teaches: A method (Fig.7), comprising:
creating a III-nitride-based decomposition layer (DL) (buffer layer 22, Fig.12, [0103] “III-V buffer layers can be grown on a Si substrate”; [0039] “ preparation method is applicable in a variety of materials, including C, Si, Ge, Sn, nitride”; [0076] “below the melting point of the buffer layer, grow a second crystal layer 24 on the buffer layer 22”) on or above a substrate (first crystal layer 20, Fig. 12, [0016] “the first crystal layer is a semiconductor substrate”).
Note: Examiner interprets the meaning of ‘decomposition’ as the breakdown of the composition of a material. As layer 22 is turned into an amorphous state by melting, the material is decomposed. Further, Wang discloses a material composition of III-V buffer layers which is a material made from elements in Group III and Group V of the periodic table. Wang explicitly teaches that the preparation method involves Group V element, nitride [0039]. Therefore, Wang meets the limitation of III-nitride-based materials.
creating a III-nitride-based decomposition stop layer (DSL) (second crystal layer 24, [0039]; [0080] “material of the second crystal layer 24 can be selected from anyone of the C, Si, Ge, Sn, binary and multiple semiconductors, oxides, and other inorganic crystals”) on or above the III-nitride-based DL (buffer layer 22, Fig.12), wherein the III-nitride-based DL (buffer layer 22), but not the III-nitride-based DSL (second crystal layer 24), is decomposed by an increase in temperature (Fig.12, [0087] “converting to an amorphous state is achieved by raising the temperature to above the melting point of the buffer layer 22”);
Note: The decomposition layer (DL) [buffer layer 22] has a lower melting point than the DSL [second crystal layer 24] resulting in the breakdown of the DL layer while the DSL [second crystal layer 24] remains intact. Further, Wang discloses binary and multiple semiconductors which encompasses III-nitride based materials. III-V materials are made from elements in Group III and Group V of the periodic table. Wang explicitly teaches that the preparation method involves Group V element, nitride [0039]. Therefore, Wang meets the limitation of III-nitride-based materials.
creating a III-nitride-based buffer layer (template layer 26, [0039]; [0085] “the template layer 26 is selected from anyone of the C, Si, Ge, Sn, binary and multiple semiconductors, oxides, and other inorganic crystals”) on or above the III-nitride-based DSL (second crystal layer 24, Fig.12)
wherein the III-nitride-based buffer layer (template layer 26, Fig.12, [0092] “template layer upon the buffer layer performs thermal annealing and adjusts the lattice constant thereof”) is a partially strained and relaxed buffer layer ([0055] “The template layer can be strained or partially relaxed”) due to the decomposed III-nitride-based DL (buffer layer 22); and
Note: Wang discloses an embodiment where a second template layer is grown above the template layer 26, therefore template layer 26 can be considered analogous to the instant claim’s buffer layer.
growing a III-nitride-based device structure (second template layer, Fig 12, [0039]; [0085]; [0089] “grow a template layer 26 on the template layer 26 grown in the growth process of the first template layer”) on or above the III-nitride-based buffer layer (template layer 26, Fig.12), wherein the device structure achieves higher power and higher efficiency in green light emissions ([0007] “high power/high temperature transistors and light-emitting devices from green to ultraviolet band. Once again, the bottleneck to improve the performance of such devices is still high-quality substrate or template with the required lattice constants.”) as compared to the III-nitride-based device structure without the partially strained and relaxed buffer layer ([0007]). Wang discloses that a partially strained/relaxed buffer layer [template layer 26] adjusts lattice constant which improves efficiencies [0092]. Without the partially strained/relaxed buffer layer, lattice constant constraints are apparent which affects characteristics of a layer [0007].
Note: Wang discloses the second template layer can be III-V which encompasses III-nitride and is interpreted to be a device structure as it can be used as a device layer. III-V materials are made from elements in Group III and Group V of the periodic table. Wang explicitly teaches that the preparation method involves Group V element, nitride [0039]. Therefore, Wang meets the limitation of III-nitride-based materials.
As to Claim 29, Wang teaches: The method of claim 1 (Fig.7), wherein the device structure is a light emitting diode (LED) or laser diode (LD) ([0039] “The present invention is applicable in semiconductors, oxides and any other crystal heterostructures, including light emitting diodes”).
Note: The claims recite at least one of the devices listed, Wang teaches a light emitting diode which satisfies this limitation.
As to Claim 30, Wang teaches: The method of claim 29 (Fig.7), wherein the device structure including a strain relaxed template (SRT) comprised of the III-nitride-based DL (buffer layer 22) and the III-nitride- based DSL (second crystal layer 24) is grown on or above a GaN template grown on a substrate ([0107] “GaN and MN templates on a (111) Si substrate; [0110] ”GaN or AlN is sequentially grown till the required thickness is reached”; [0111]), and the substrate (first crystal layer 20, [0016] “the first crystal layer is a semiconductor substrate”) is sapphire, silicon (Si), silicon carbide (SiC), glass, III-nitride-based such as
GaN and AlN with any crystal orientation such as nonpolar and semipolar, or other materials ([0017] “Optionally, the first crystal layer is selected from anyone of the C, Si, Ge, Sn, binary and multiple semiconductors, oxides, and other inorganic crystals with arbitrarily crystal orientation”). Note: The claims recite at least one of the materials listed, Wang teaches a material including Si which satisfies this limitation.
As to Claim 31, Wang teaches: A device (Fig.12), comprising:
A III-nitride-based decomposition layer (DL) (buffer layer 22, [0039]) created on or above a substrate (first crystal layer 20, Fig. 12, [0016] “the first crystal layer is a semiconductor substrate”);
Note: Examiner interprets the meaning of ‘decomposition’ as the breakdown of the composition of a material. As layer 22 is turned into an amorphous state by melting, the material is decomposed. Further, Wang discloses a material composition of III-V buffer layers which is a material made from elements in Group III and Group V of the periodic table. Wang explicitly teaches that the preparation method involves Group V element, nitride [0039]. Therefore, Wang meets the limitation of III-nitride-based materials.
a III-nitride-based decomposition stop layer (DSL) (second crystal layer 24, [0080] “material of the second crystal layer 24 can be selected from anyone of the C, Si, Ge, Sn, binary and multiple semiconductors, oxides, and other inorganic crystals”) created on or above the III-nitride-based DL (buffer layer 22, Fig.12), wherein the III-nitride-based DL (buffer layer 22), but not the III-nitride-based DSL (second crystal layer 24),
is decomposed by an increase in temperature (Fig.12, [0087] “converting to an amorphous state is achieved by raising the temperature to above the melting point of the buffer layer 22”); a III-nitride-based buffer layer (template layer 26, [0039]; [0085] “the template layer 26 is selected from anyone of the C, Si, Ge, Sn, binary and multiple semiconductors, oxides, and other inorganic crystals”) created on or above the III-nitride-based DSL (second crystal layer 24, Fig.12),
Note: The decomposition layer (DL) [buffer layer 22] has a lower melting point than the DSL [second crystal layer 24] resulting in the breakdown of the DL layer while the DSL [second crystal layer 24] remains intact. Further, Wang discloses binary and multiple semiconductors which encompasses III-nitride based materials. III-V materials are made from elements in Group III and Group V of the periodic table. Wang explicitly teaches that the preparation method involves Group V element, nitride [0039]. Therefore, Wang meets the limitation of III-nitride-based materials.
wherein the III-nitride-based buffer layer (template layer 26, Fig.12, [0092] “template layer upon the buffer layer performs thermal annealing and adjusts the lattice constant thereof”) is a partially strained and relaxed buffer layer ([0055] “The template layer can be strained or partially relaxed”) due to the decomposed III-nitride-based DL (buffer layer 22); and
Note: Wang discloses an embodiment where a second template layer is grown above the template layer 26, therefore template layer 26 can be considered analogous to the instant claim’s buffer layer.
a III-nitride-based device structure (second template layer, Fig 12, [0089] “grow a template layer 26 on the template layer 26 grown in the growth process of the first template layer”; [0039]) grown on or above the III-nitride-based buffer layer (template layer 26, Fig.12), wherein the device structure achieves higher power and higher efficiency in green light emissions ([0007] “high power/high temperature transistors and light-emitting devices from green to ultraviolet band. Once again, the bottleneck to improve the performance of such devices is still high-quality substrate or template with the required lattice constants.”) as compared to the III-nitride-based device structure without the partially strained and relaxed buffer layer ([0007]). Wang discloses that a partially strained/relaxed buffer layer [template layer 26] adjusts lattice constant which improves efficiencies [0092]. Without the partially strained/relaxed buffer layer, lattice constant constraints are apparent which affects characteristics of a layer [0007].
Note: Wang discloses the second template layer can be III-V which encompasses III-nitride and is interpreted to be a device structure as it can be used as a device layer. III-V materials are made from elements in Group III and Group V of the periodic table. Wang explicitly teaches that the preparation method involves Group V element, nitride [0039]. Therefore, Wang meets the limitation of III-nitride-based materials.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 2 is/are rejected under 35 U.S.C 103 as being unpatentable over Wang as being applied to Claim(s) 1 and 29-31 above, and in further view of Hanser et al. (US 20090081857 A1) hereinafter Hanser.
As to Claim 2, Wang teaches: The method of claim 1 (Fig.7),
Wang does not explicitly teach: wherein a step-flow surface morphology is observed in at least a 5 μm x 5 μm area of a top surface of the III-nitride-based device structure by atomic force microscopy measurement. Wang does teach a III-nitride based device structure but fails to disclose a step-flow morphology.
However, in an analogous art, Hanser teaches: wherein a step-flow surface morphology is observed ([0049] “surface showed a generally smooth, step flow-type surface”) in at least a 5 μm x 5 μm area ([0049] “5 μm×5 μm AFM scan”) of a top surface of the III-nitride-based device structure ([0004] “optoelectronic devices (such as light emitting diodes (LEDs), laser diodes (LDs) and photodetectors) and electronic devices (such as diodes and field effect transistors (FETs)) composed of III-V nitride compounds”) by atomic force microscopy measurement ([0049] “AFM characterization was performed on the re-growth surface of the m-plane samples”).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to apply the teaching of Hanser to supplement the growth process as taught by Wang to include observing the morphology of top surface of the III-nitride-based device. One would be motivated to do so to ensure dislocation density and strain-induced effects have been reduced to produce efficient LEDs and LDs of short wavelengths (Hanser, [0006]; [0009]).
Claim(s) 3 is/are rejected under 35 U.S.C 103 as being unpatentable over Wang as being applied to Claim(s) 1, 29-31 above, and in further view of Yang et al. (CN 103633199 A) hereinafter Yang.
As to Claim 3, Wang teaches: The method of claim 1 (Fig.7),
Wang does not explicitly teach: wherein the III-nitride-based DL is InGaN or multiple periods of an InGaN / GaN superlattice (SL) grown at a temperature between 700°C and 800°C. Wang does teach a III-nitride-based DL [buffer layer 22] but fails to disclose the DL being composed of InGaN or multiple periods of InGaN/GaN superlattice grown at a temperature between 700°C and 800°C.
However, in an analogous art, Yang teaches: wherein the III-nitride-based DL (an indium component thin III-nitride alloy layer 202, [0036] “temperature-raising annealing, wherein the inner portion of the thin-group III nitride alloy layer 202 containing the indium composition becomes a porous thin group III nitride weak bonding layer 204”) is InGaN ([0035] “thin group III nitride alloy layer 202 containing the indium component is limited to one of InxGa1-xN, InxAl1-xN, In xAlyGa1-xyN”) or multiple periods of an InGaN / GaN superlattice (SL) grown at a temperature between 700°C and 800°C ([0035] “the growing temperature is 450 ℃ to 950 ℃”). A prima facie case of obviousness exists where the claimed ranges or amounts “overlap or lie inside ranges disclosed by the prior art”. See MPEP 2144.05. Yang discloses that a person skilled in the art can determine the temperature conditions of growing the layer based on its material characteristics [0049].
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to apply the teaching of Yang to modify the material composition and growth temperature range of the DL as taught by Wang. One would be motivated to do so as GaN materials are cost-efficient, have a large area without cracks, and high crystal quality growth (Yang, [0004]). Further, one would be motivated to grow the DL layer at the given temperature range to improve the material quality and device fabrication efficiency (Yang, [0006]).
Allowable Subject Matter
Claims 4-28 would be allowable if rewritten to be independent and amended to overcome the objection(s) set forth in this Office action. The following is an Examiner’s statement of reasons for allowance.
As to Claim 4, Wang/Yang teaches: The method of claim 1 (Wang, Fig.12), wherein the III-nitride-based DSL (Wang, second crystal layer 24) is n-type
GaN (Yang, [0053] “low-temperature thin gallium nitride layer 201”) or an n-type InxGa1-xN / GaN SL with x < 0.05.
Wang/Yang fails to disclose the following limitations: n-type GaN or an n-type InxGa1-xN / GaN SL with x < 0.05. Wang/Yang both teach III-nitride-based DSL layer [Wang, second crystal layer 24; Yang, low-temperature thin gallium nitride layer 201], but they both fail to disclose the III-nitride-based DSL layer as n-type GaN or an n-type InxGa1-xN / GaN SL with x < 0.05. Yang does disclose the GaN composition of the DSL but remains silent about DSL being n-type.
Furthermore, none of the cited prior art of record, taken alone or in combination of one another, discloses or renders obvious the method as described above in full context of Claim 4 of the instant application. Therefore, Claim 4 contains allowable subject matter.
Regarding Claims 5-28, due to their dependence upon an already allowable claim (i.e., Claim 4), they are further deemed allowable subject matter, pending resolution of dependency and the above-stated claim objections.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mashal Ahmed whose telephone number is (571)270-1754. The examiner can normally be reached M-F, 9AM to 5 PM.
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/MASHAL AHMED/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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