Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on July 19, 2024 was reviewed and considered by the examiner. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: 103 and 104 in Fig. 3. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 3 & 7 are objected to because of the following informalities: the last line of this claim, in the phrase "the buffer unit is a source follower…", the "a" before "source follower" should be "the", as "source follower" was introduced in the line above within the claim. Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-3 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2 of copending Application No. 17/911,019 and 17/907,870 (reference application), in view of Hiroshi et al. (JPS611104A, as cited by applicant), hereinafter Hiroshi, further in view of Hikari (JPS575410A, as cited by applicant), hereinafter Hikari. Although the claims at issue are not identical, they are not patentably distinct from each other because of the anticipating limitations in bold and underlined, as shown in Table 1 below.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Instant Application 18/730,860
U.S. Copending Application 17/907,870
(App’870)
U.S. Copending Application 17/911,019
(App’019)
Claim 1:
A current-voltage conversion device comprising:
an amplification unit that includes at least three stages each of which is formed of electronic elements, a target current being supplied to a first-stage, and amplifies a voltage generated by the target current; and
a buffer unit that is connected to the amplification unit and outputs the converted voltage, wherein
a common first voltage is supplied to all the electronic elements, and
a second voltage different from the first voltage is supplied to an input of the target current of the first-stage electronic element, and
the amplification unit includes a plurality of feedback circuits connected in series that feeds back an output voltage from a final-stage of the amplification unit to the input, and each of the plurality of feedback circuits includes a resistive element.
Claim 2:
The current-voltage conversion device according to claim 1, wherein the current-voltage conversion device operates in a cryogenic environment of 4 K or less.
Claim 3:
The current-voltage conversion device according to claim 1, wherein the electronic element is a field effect transistor, the amplification unit is a four-stage common source voltage amplification stage, and a final-stage constitutes a source follower, and the buffer unit is a source follower constituted by the electronic element.
Claim 1:
A current-to-voltage converter comprising:
an amplification unit having at least three stages each including an electronic element and configured to convert a target current, which is fed to a first stage, to a voltage while feeding back an output signal of a final stage to the first stage; and
a buffer unit connected to the amplification unit and configured to output the converted voltage, wherein the electronic element is a field-effect transistor (FET) adapted to operation at a temperature of 150 K or less.
Claim 2:
The current-to-voltage converter according to claim 1, wherein the amplification unit has four common source voltage amplifier stages, and the final stage constitutes a source follower, and the buffer unit is a source follower that includes the electronic element.
Claim 1:
A current-to-voltage converter comprising:
an amplification unit having at least three stages each including an electronic element and configured to convert a target current, which is fed to a first stage, to a voltage while feeding back an output signal of a final stage to the first stage; and
a buffer unit connected to the amplification unit and configured to output the converted voltage, wherein the electronic element is a field-effect transistor (FET) adapted to operation at a temperature of 150 K or less, a gate of the FET is connected to a ground potential, and a single common power supply is fed to each FET.
Claim 2:
The current-to-voltage converter according to claim 1, wherein the amplification unit has four common source voltage amplifier stages, and the final stage constitutes a source follower, and the buffer unit is a source follower that includes the electronic element.
Table 1
App’870 fails to teach a common first voltage is supplied to all the electronic elements, and a second voltage different from the first voltage is supplied to an input of the target current of the first-stage electronic element, and the amplification unit includes a plurality of feedback circuits connected in series, and each of the plurality of feedback circuits includes a resistive element.
However, Hiroshi further teaches a common first voltage is supplied to all the electronic elements (drain voltage supplied to field-effect transistors in all the stages), and a second voltage (bias voltage Vg1) different from the first voltage is supplied to an input of the target current of the first-stage electronic element (gate of the first-stage transistor). Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified App’870 to incorporate the teachings of Hiroshi, for the purpose of optimizing noise figure.
App’870, in view of Hiroshi, fails to teach the amplification unit includes a plurality of feedback circuits connected in series, and each of the plurality of feedback circuits includes a resistive element.
However, Hikari further teaches a plurality of feedback circuits (C1/C2/R2/R3) connected in series that feeds back an output voltage from a final-stage of the amplification unit to the input (output of A1 through feedback circuits to inverting of A1), and each of the plurality of feedback circuits includes a resistive element (R2/R3). Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified App’870, in view of Hiroshi, to incorporate the teachings of Hikari, for the purpose of configuring the feedback circuit.
App’019 fails to teach a second voltage different from the first voltage is supplied to an input of the target current of the first-stage electronic element, and the amplification unit includes a plurality of feedback circuits connected in series, and each of the plurality of feedback circuits includes a resistive element.
However, Hiroshi further teaches a second voltage (bias voltage Vg1) different from the first voltage is supplied to an input of the target current of the first-stage electronic element (gate of the first-stage transistor). Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified App’019 to incorporate the teachings of Hiroshi, for the purpose of optimizing noise figure.
App’019, in view of Hiroshi, fails to teach the amplification unit includes a plurality of feedback circuits connected in series, and each of the plurality of feedback circuits includes a resistive element.
However, Hikari further teaches a plurality of feedback circuits (C1/C2/R2/R3) connected in series that feeds back an output voltage from a final-stage of the amplification unit to the input (output of A1 through feedback circuits to inverting of A1), and each of the plurality of feedback circuits includes a resistive element (R2/R3). Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified App’019, in view of Hiroshi, to incorporate the teachings of Hikari, for the purpose of configuring the feedback circuit.
Claims 1-3 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2 of U.S. Patent No. 12,216,143 in view of Hiroshi, further in view of Hikari. Although the claims at issue are not identical, they are not patentably distinct from each other because of the anticipating limitations in bold, as shown in Table 2 below.
Instant Application 18/730,860
U.S. Patent Number 12,216,143
(Pat’143)
Claim 1:
A current-voltage conversion device comprising:
an amplification unit that includes at least three stages each of which is formed of electronic elements, a target current being supplied to a first-stage, and amplifies a voltage generated by the target current; and
a buffer unit that is connected to the amplification unit and outputs the converted voltage, wherein
a common first voltage is supplied to all the electronic elements, and a second voltage different from the first voltage is supplied to an input of the target current of the first-stage electronic element, and
the amplification unit includes a plurality of feedback circuits connected in series that feeds back an output voltage from a final-stage of the amplification unit to the input, and each of the plurality of feedback circuits includes a resistive element.
Claim 2:
The current-voltage conversion device according to claim 1, wherein the current-voltage conversion device operates in a cryogenic environment of 4 K or less.
Claim 3:
The current-voltage conversion device according to claim 1, wherein the electronic element is a field effect transistor, the amplification unit is a four-stage common source voltage amplification stage, and a final-stage constitutes a source follower, and the buffer unit is a source follower constituted by the electronic element.
Claim 1:
A current-to-voltage converter comprising:
an amplification unit having at least three stages each including a field-effect transistor (FET), a target current being fed to a first stage, a final stage constituting a source follower configured to feed back an output signal to the first stage, the amplification unit being configured to convert the target current to a voltage; and a buffer unit that is connected to the amplification unit, constitutes a source follower including a FET, and is configured to output the converted voltage, wherein each FET is adapted to operation at a temperature of 150 K or less.
Claim 2:
The current-to-voltage converter according to claim 1, wherein the amplification unit has four common source voltage amplifier stages.
Table 2
Pat’143 fails to teach a common first voltage is supplied to all the electronic elements, and a second voltage different from the first voltage is supplied to an input of the target current of the first-stage electronic element, and the amplification unit includes a plurality of feedback circuits connected in series, and each of the plurality of feedback circuits includes a resistive element.
However, Hiroshi further teaches a common first voltage is supplied to all the electronic elements (drain voltage supplied to field-effect transistors in all the stages), and a second voltage (bias voltage Vg1) different from the first voltage is supplied to an input of the target current of the first-stage electronic element (gate of the first-stage transistor). Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Pat’143 to incorporate the teachings of Hiroshi, for the purpose of optimizing noise figure.
Pat’143, in view of Hiroshi, fails to teach the amplification unit includes a plurality of feedback circuits connected in series, and each of the plurality of feedback circuits includes a resistive element.
However, Hikari further teaches a plurality of feedback circuits (C1/C2/R2/R3) connected in series that feeds back an output voltage from a final-stage of the amplification unit to the input (output of A1 through feedback circuits to inverting of A1), and each of the plurality of feedback circuits includes a resistive element (R2/R3). Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Pat’143, in view of Hiroshi, to incorporate the teachings of Hikari, for the purpose of configuring the feedback circuit.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 2 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The examiner is unclear what the "4K or less" refers to in this claim. For examining purposes, the examiner assumes the phrase is referring to temperature.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 and 7-10 are rejected under 35 U.S.C. 103 as being unpatentable over Hashisaka et al. (WO 2021186651 A1, as cited by applicant), hereinafter Hashisaka, in view of Hiroshi, and further in view of Hikari.
Regarding Claim 1, Hashisaka teaches a current-voltage conversion device (Hashisaka, Fig. 3) comprising: an amplification unit (Hashisaka, Fig. 3, 101) that includes at least three stages (Hashisaka, Fig. 3, stages that include H1/H2/H3/H4) each of which is formed of electronic elements (Hashisaka, Fig. 3, transistors), a target current being supplied to a first-stage (Hashisaka, Fig. 3, input current from 103 to gate of H1), and amplifies a voltage generated by the target current (Hashisaka, page 4, paragraph 4 starting with Fig. 3); and a buffer unit (Hashisaka, Fig. 3, 102) that is connected to the amplification unit and outputs the converted voltage, wherein a common first voltage (Hashisaka, Fig. 3, 105) is supplied to all the electronic elements.
Hashisaka fails to teach a second voltage different from the first voltage is supplied to an input of the target current of the first-stage electronic element.
However, Hiroshi teaches a second voltage (Hiroshi, bias voltage Vg1) different from the first voltage is supplied to an input of the target current of the first-stage electronic element (Hiroshi, gate of the first-stage transistor). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Hashisaka to incorporate the teachings of Hiroshi, for the purpose of optimizing noise figure.
Hashisaka, in view of Hiroshi, fails to teach a plurality of feedback circuits, included in the amplification unit, connected in series that feeds back an output voltage from a final-stage of the amplification unit to the input, and each of the plurality of feedback circuits includes a resistive element.
However, Hikari teaches a plurality of feedback circuits (Hikari, C1/C2/R2/R3) connected in series that feeds back an output voltage from a final-stage of the amplification unit to the input (Hikari, output of A1 through feedback circuits to inverting of A1), and each of the plurality of feedback circuits includes a resistive element (Hikari, R2/R3). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Hashisaka, in view of Hiroshi, to incorporate the teachings of Hikari, for the purpose of configuring the feedback circuit.
Regarding Claim 2, Hashisaka, in view of Hiroshi, further in view of Hikari, teaches the current-voltage conversion device according to claim 1, wherein the current-voltage conversion device operates in a cryogenic environment of 4 K or less (Hashisaka, Abstract; page 4, paragraph 6).
Regarding Claim 3, Hashisaka, in view of Hiroshi, further in view of Hikari, teaches the current-voltage conversion device according to claim 1, wherein the electronic element is a field effect transistor (Hashisaka, Fig. 3, H1/H2/H3/H4), the amplification unit is a four-stage common source voltage amplification stage (Hashisaka, Fig. 3, stages that include H1/H2/H3/H4), and a final-stage constitutes a source follower (Hashisaka, Fig. 3, 102), and the buffer unit is a source follower constituted by the electronic element .
Regarding Claim 4, Hashisaka, in view of Hiroshi, further in view of Hikari, teaches the current-voltage conversion device according to claim 3, wherein the field effect transistor is a high-electron-mobility transistor (HEMT) [Hashisaka, Abstract; page 5, paragraph 2].
Regarding Claim 5, Hashisaka, in view of Hiroshi, further in view of Hikari, teaches the current-voltage conversion device according to claim 1, wherein each of the plurality of feedback circuits further includes a capacitor (Hikari, C1/C2) in parallel with the resistive element.
Regarding Claim 7, Hashisaka, in view of Hiroshi, further in view of Hikari, teaches the current-voltage conversion device according to claim 2, wherein the electronic element is a field effect transistor (Hashisaka, Fig. 3, H1/H2/H3/H4), the amplification unit is a four-stage common source voltage amplification stage (Hashisaka, Fig. 3, stages that include H1/H2/H3/H4), and a final-stage constitutes a source follower (Hashisaka, Fig. 3, 102), and the buffer unit is a source follower constituted by the electronic element.
Regarding Claim 8, Hashisaka, in view of Hiroshi, further in view of Hikari, teaches the current-voltage conversion device according to claim 2, wherein each of the plurality of feedback circuits further includes a capacitor (Hikari, C1/C2) in parallel with the resistive element.
Regarding Claim 9, Hashisaka, in view of Hiroshi, further in view of Hikari, teaches the current-voltage conversion device according to claim 3, wherein each of the plurality of feedback circuits further includes a capacitor (Hikari, C1/C2) in parallel with the resistive element.
Regarding Claim 10, Hashisaka, in view of Hiroshi, further in view of Hikari, teaches the current-voltage conversion device according to claim 4, wherein each of the plurality of feedback circuits further includes a capacitor (Hikari, C1/C2) in parallel with the resistive element.
Claims 6 and 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over Hashisaka, in view of Hiroshi, further in view of Hikari, and further in view of Abdo et al. (WO 2015057839 A1), hereinafter Abdo.
Regarding Claim 6, Hashisaka, in view of Hiroshi, further in view of Hikari, teaches all the elements of the current invention as stated above except wherein the target current reflects a state of a quantum bit. However, Abdo teaches wherein the target current reflects a state of a quantum bit (Abdo, Fig. 1, paragraphs 0047-0048).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Hashisaka, in view of Hiroshi, further in view of Hikari, to incorporate the teachings of Abdo, for the purpose of reduce the noise feedback at extremely low temperatures.
Regarding Claim 11, Hashisaka, in view of Hiroshi, further in view of Hikari, teaches all the elements of the current invention as stated above wherein the target current reflects a state of a quantum bit. However, Abdo teaches wherein the target current reflects a state of a quantum bit (Abdo, Fig. 1, paragraphs 0047-0048).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Hashisaka, in view of Hiroshi, further in view of Hikari, to incorporate the teachings of Abdo, for the purpose of reduce the noise feedback at extremely low temperatures.
Regarding Claim 12, Hashisaka, in view of Hiroshi, further in view of Hikari, teaches all the elements of the current invention as stated above except wherein the target current reflects a state of a quantum bit. However, Abdo teaches wherein the target current reflects a state of a quantum bit (Abdo, Fig. 1, paragraphs 0047-0048).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Hashisaka, in view of Hiroshi, further in view of Hikari, to incorporate the teachings of Abdo, for the purpose of reduce the noise feedback at extremely low temperatures.
Regarding Claim 13, Hashisaka, in view of Hiroshi, further in view of Hikari, teaches all the elements of the current invention as stated above except wherein the target current reflects a state of a quantum bit. However, Abdo teaches wherein the target current reflects a state of a quantum bit (Abdo, Fig. 1, paragraphs 0047-0048).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Hashisaka, in view of Hiroshi, further in view of Hikari, to incorporate the teachings of Abdo, for the purpose of reduce the noise feedback at extremely low temperatures.
Regarding Claim 14, Hashisaka, in view of Hiroshi, further in view of Hikari, teaches all the elements of the current invention as stated above wherein the target current reflects a state of a quantum bit. However, Abdo teaches wherein the target current reflects a state of a quantum bit (Abdo, Fig. 1, paragraphs 0047-0048).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Hashisaka, in view of Hiroshi, further in view of Hikari, to incorporate the teachings of Abdo, for the purpose of reduce the noise feedback at extremely low temperatures.
Conclusion
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/Amit R Bhatia/Examiner, Art Unit 2842
/LINCOLN D DONOVAN/Supervisory Patent Examiner, Art Unit 2842