Prosecution Insights
Last updated: April 19, 2026
Application No. 18/730,776

INTEGRATED POWER BLOCK

Non-Final OA §103
Filed
Jul 21, 2024
Examiner
BEHM, HARRY RAYMOND
Art Unit
2838
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Moksha Integrated Power LLC
OA Round
1 (Non-Final)
79%
Grant Probability
Favorable
1-2
OA Rounds
2y 7m
To Grant
87%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allow Rate
913 granted / 1150 resolved
+11.4% vs TC avg
Moderate +7% lift
Without
With
+7.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
37 currently pending
Career history
1187
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
49.6%
+9.6% vs TC avg
§102
34.9%
-5.1% vs TC avg
§112
8.9%
-31.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1150 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement (IDS) submitted on 7/21/2024 has been considered by the examiner. Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the case comprising an insulated outer shell and an insulating internal material, as in Claim 1, must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Objections Claims 1-6 are objected to because of the following informalities: Claim 1 must end in a period. Appropriate correction is required. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-2 are rejected under 35 U.S.C. 103 as being unpatentable over Bendre (US 2008/0298103) in view of (CN 107018632). With respect to claim 1, Bendre discloses a system (Fig. 1 102) for digital power conversion, comprising: a control system (Fig. 27 2702,2706), wherein the control system is configured by a software framework (Fig. 27 2708) to output pulse-width modulated (PWM) signals (Fig. 4B gate signals are pulse width modulated according to zero common mode modulation) and input/output (I/O) signals (Fig. 27 INPUTS/OUTPUTS); a power system (Fig. 4B 400) , wherein the power system is configured to receive (Fig. 17B GATE SIGNALS) and operate in accordance with the PWM signals; a DC bus system (Fig. 4B DC+,DC-) and electrically coupled to the power system, wherein the DC bus system comprises one or more DC buses, each individually comprising a positive DC bus (Fig. 4B DC+) and a negative DC bus (Fig. 4B DC-), and wherein the positive DC bus and the negative DC bus of each of the one or more DC buses are each externally accessible (Fig. 1 internal DC bus connects to 104) via a corresponding pair of DC terminals comprising a positive DC terminal and a negative DC terminal; and an AC bus system (Fig. 4B U,V,W) electrically coupled to the power system, wherein the AC bus system comprises one or more AC buses, and wherein each of the one or more AC buses is externally (Fig. 1 AC bus connects to 106) accessible via an AC terminal. Bendre remains silent as to the details of the case enclosing the control system, power system and DC and AC bus systems. The ‘632 invention discloses a power cabinet comprising an insulating outer shell (Fig. 2 7) and an insulating internal material (Fig. 2 5). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement a system for digital power conversion, comprising: a case comprising an insulating outer shell and an insulating internal material; a control system housed in the case, wherein the control system is configured by a software framework to output pulse-width modulated (PWM) signals and input/output (I/O) signals; a power system housed in the case, wherein the power system is configured to receive and operate in accordance with the PWM signals; a DC bus system housed in the case and electrically coupled to the power system, wherein the DC bus system comprises one or more DC buses, each individually comprising a positive DC bus and a negative DC bus, and wherein the positive DC bus and the negative DC bus of each of the one or more DC buses are each externally accessible via a corresponding pair of DC terminals comprising a positive DC terminal and a negative DC terminal; and an AC bus system housed in the case and electrically coupled to the power system, wherein the AC bus system comprises one or more AC buses, and wherein each of the one or more AC buses is externally accessible via an AC terminal, in order to provide internal and external insulation to protect the internal components from condensation and protect the device from the external environment as well as protect the user from shock hazard. With respect to claim 2, Bendre in view of ‘632 make obvious the system for digital power conversion of claim 1, wherein the case further comprises a conductive internal lining (Fig. 2 4) disposed between the insulating outer shell and the insulating internal material, configured to act as a Faraday cage (Fig. 1 4 blocks external radiation). Claim(s) 3 is rejected under 35 U.S.C. 103 as being unpatentable over Bendre (US 2008/0298103) in view of (CN 107018632) and further in view of Hassbjer (2008/0168196). With respect to claim 3, Bendre in view of ‘632 make obvious the system for digital power conversion of claim 1, wherein the control system comprises a digital signal processing subsystem (Fig. 27 2702,2706) comprising one or more digital signal processing circuits (Fig. 27 2702,2706), wherein the digital signal processing subsystem is configured to generate and transmit the PWM signals (Fig. 17B GATE SIGNALS) and the I/O signals (Fig. 27 INPUTS/OUTPUTS). Bendre remains silent as the I/O communications, but the use of serial communication and high density connectors were well known before the effective filing date of the invention. Hassbjer discloses wherein the I/O signals comprise serial/communication I/O signals (paragraph 40), and wherein the control system further comprises an externally (paragraph 38) accessible high density connector (Fig. 2 201) electrically coupled to at least one of the I/O signals (Fig. 2 1-50). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement wherein the I/O signals comprise serial/communication I/O signals, and wherein the control system further comprises an externally accessible high density connector electrically coupled to at least one of the I/O signals, in order to permit communications to the system to perform troubleshooting, maintenance and upgrades. Claim(s) 4 is rejected under 35 U.S.C. 103 as being unpatentable over Bendre (US 2008/0298103) in view of (CN 107018632) and further in view of Olsson (US 9,574,760) With respect to claim 4, Bendre in view of ‘632 make obvious the system for digital power conversion of claim 1 as set forth above, and remain silent as to providing signal isolation, which was well known before the effective filing date of the claimed invention. Olsson discloses wherein the control system further comprises a communication interface subsystem (Fig. 17 2732,2734) and one or more externally accessible user interface connectors (Fig. 1 108), the communication interface subsystem comprises a signal isolator (Fig. 27 2734), and wherein the communication interface subsystem electrically couples the serial/communication I/O signals (paragraph 136) to the one or more externally accessible user interface connectors. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement wherein the control system further comprises a communication interface subsystem and one or more externally accessible user interface connectors, the communication interface subsystem comprises a signal isolator, and wherein the communication interface subsystem electrically couples the serial/communication I/O signals to the one or more externally accessible user interface connectors. Claim(s) 5 is rejected under 35 U.S.C. 103 as being unpatentable over Bendre (US 2008/0298103) in view of (CN 107018632) and further in view of Green (US 2006/0006811). With respect to claim 5, Bendre in view of ‘632 make obvious the system for digital power conversion of claim 1 as set forth above, and further discloses a switching device subsystem (Fig. 4B Qu1-Qw6) comprising one or more semiconductor transistor circuits, each semiconductor transistor circuit being electrically coupled (Fig.17B GATE SIGNALS) to the gate driver subsystem (Fig. 17B 1758), and the switching device subsystem being electrically coupled to the DC bus system (Fig. 4B DC+,DC-) or the AC bus system (Fig. 4B U,V,W). Bendre remains silent as to the details of the logic power subsystem which was well known before the effective filing date of the invention. Green discloses wherein the power system comprises: a logic power subsystem (Fig. 1 RS,CVCC1) comprising one or more logic power circuits, electrically coupled to the DC bus system (Fig. 1 DC BUS+); a power failsafe subsystem (Fig. 2 UVLO, inverter, RS latch and AND gate for blocking 32), electrically coupled to the logic power subsystem (Fig. 2 VCC) and comprising sensing elements (Fig. 2 UVLO senses VCC); a gate driver subsystem (Fig. 2 20,30,32) comprising one or more gate driver circuits, each gate driver circuit being electrically coupled to the power failsafe subsystem (Fig. 2 blocking AND gate driving latch 32, blocking AND gate driving 20) and to the PWM signals (Fig. 2 T latch); and a switching device subsystem (Fig. 1 Q1,Q2) comprising one or more semiconductor transistor circuits, each semiconductor transistor circuit being electrically coupled (Fig. 2 HO,LO) to the gate driver subsystem, and the switching device subsystem being electrically coupled (Fig. 1 DC Bus+) to the DC bus system or the AC bus system. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement wherein the power system comprises: a logic power subsystem comprising one or more logic power circuits, electrically coupled to the DC bus system; a power failsafe subsystem, electrically coupled to the logic power subsystem and comprising sensing elements; a gate driver subsystem comprising one or more gate driver circuits, each gate driver circuit being electrically coupled to the power failsafe subsystem and to the PWM signals; and a switching device subsystem comprising one or more semiconductor transistor circuits, each semiconductor transistor circuit being electrically coupled to the gate driver subsystem, and the switching device subsystem being electrically coupled to the DC bus system or the AC bus system, in order to protect and drive the switching devices as was well known in the art. Claim(s) 6 is rejected under 35 U.S.C. 103 as being unpatentable over Bendre (US 2008/0298103) in view of (CN 107018632), Green (US 2006/0006811) and further in view of DeLaFuente (US 2019/0383455). With respect to claim 6, Bendre in view of ‘632 and Green make obvious the system for digital power conversion of claim 5 as set forth above, and remain silent as to implementing an IMS layer, which was known before the effective filing date of the claimed invention. DeLaFuente discloses wherein the system further comprises an insulated metal substrate layer (paragraph 9), and wherein the insulated metal substrate layer (Fig. 1 41) is externally accessible (Fig. 1 61). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement wherein the power system further comprises an insulated metal substrate layer bonded to the power system, and wherein the insulated metal substrate layer is externally accessible and is thermally coupled to at least one of the one or more semiconductor transistors, in order to remove the heat from the transistors and provide the user access to the ground for troubleshooting and maintenance. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to HARRY RAYMOND BEHM whose telephone number is (571)272-8929. The examiner can normally be reached M-F: 8-5 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu Tran can be reached at 571-270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HARRY R BEHM/Primary Examiner, Art Unit 2838
Read full office action

Prosecution Timeline

Jul 21, 2024
Application Filed
Mar 06, 2026
Non-Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
79%
Grant Probability
87%
With Interview (+7.3%)
2y 7m
Median Time to Grant
Low
PTA Risk
Based on 1150 resolved cases by this examiner. Grant probability derived from career allow rate.

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