DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 8-10, 13, 15-18, are rejected under 35 U.S.C. 103 as being unpatentable over Toledo et al. U.S. Patent Application publication 2025/0254119 in view of Budhia et al. U.S. Patent publication 11,895,015.
Claim 1,
Toledo discloses
An apparatus for a network device, comprising:
first logic configured to generate first codes for a packet (para 0059- applies a simple hash to sum the 5-tuple of a packet header), and
receive a second code that represents a number of paths through a network between the network device and a destination of the packet (para 0057- discloses using the total number of paths to determine a selected path);
first circuits, coupled to the first logic, each configured to perform a comparison of one of the first codes with the second code and provide an output depending on the comparison (para 0034- discloses a plurality of circuitry, para 0064- discloses ECMP routing scheme 490 depicts a simple hash function that sums the values of 5-tuple components (e.g., source port, destination port, source IP address, and destination IP address) and then applies the modulo operation to determine a number identifying a particular path, where the modulo is based on the number of available paths (here, 27, numbered from 0-26). Some of the possible paths are depicted in paths 495, including paths 410 and 426.).
Although Toledo discloses substantial limitations of the claim invention, it fails to explicitly disclose
a second circuit, coupled to the first logic and the first circuits, configured to select the output of one of the first circuits as a third code that represents one of the paths.
In an analogous art, Budhia discloses
a second circuit, coupled to the first logic and the first circuits, configured to select the output of one of the first circuits as a third code that represents one of the paths. (col 28, lines 20-30- circuitry, fig. 3B, col 24, lines 13-24- discloses selecting an output of a plurality of algorithms to determine a selected path)
One of ordinary skill in the art before the effective filing date of the invention would find it obvious to combine the path selection of Budhia with the Toledo system to produce the predictable result of selecting a path from a plurality based on performance.
Claim 2,
wherein each of the first circuits includes a comparator configured to perform the comparison and generate an output being a result of the comparison .(Toledo para 0064- disclose the comparison of the 5-tuple to the number of paths to generate a hash)
Claim 8,
Toledo discloses
A network device, comprising:
a packet processor configured to receive a packet (para 0020- discloses receiving packet in data flow);
first logic, coupled to the packet processor, configured to generate first codes for the packet (para 0059- applies a simple hash to sum the 5-tuple of a packet header),
receive from a memory a second code that represents a number of paths through a network between the network device and a destination (para 0057- discloses using the total number of paths to determine a selected path), and
first circuits, coupled to the first logic, each configured to perform a comparison of one of the first codes with the second code and provide an output depending on the comparison (para 0034- discloses a plurality of circuitry, para 0064- discloses ECMP routing scheme 490 depicts a simple hash function that sums the values of 5-tuple components (e.g., source port, destination port, source IP address, and destination IP address) and then applies the modulo operation to determine a number identifying a particular path, where the modulo is based on the number of available paths (here, 27, numbered from 0-26). Some of the possible paths are depicted in paths 495, including paths 410 and 426.).
Although Toledo discloses substantial limitations of the claim invention, it fails to explicitly disclose
provide a third code that represents one of the paths to the packet processor; and a second circuit, coupled to the first logic and the first circuits, configured to select the output of one of the first circuits as the third code.
In an analogous art, Budhia discloses
provide a third code that represents one of the paths to the packet processor (col 24-an algorithm selector 310 may be implemented or controlled to select the output of the specific load balancing or path selection algorithm 308 in response to receiving a specific load balancing (or path selection) algorithm select in algorithm controls sent or provided by the load balancing algorithm controller 306. The packet processor is mapped to the switch device in fig. 2. ); and
a second circuit, coupled to the first logic and the first circuits, configured to select the output of one of the first circuits as the third code (col 28, lines 20-30- circuitry, fig. 3B, col 24, lines 13-24- discloses selecting an output of a plurality of algorithms to determine a selected path).
One of ordinary skill in the art before the effective filing date of the invention would find it obvious to combine the path selection of Budhia with the Toledo system to produce the predictable result of selecting a path from a plurality based on performance.
Claim 9,
wherein the first logic includes second logic configured to receive as an input at least a portion of the packet and generate the first codes from a hash of the input (Toledo para 0059).
Claim 10,
wherein each of the first circuits includes a comparator configured to perform the comparison and generate an output being a result of the comparison (Toledo para 0059).
Claim 13,
wherein each of the first circuits includes a multiplexer configured to perform a selection in response to the output of the comparator. (Toledo para 0059- discloses logic to perform a selection of a path, Budhia col 28, lines 27-31- disclose implementing path selection through multiplexers and logic gates.)
One of ordinary skill in the art before the effective filing date of the invention would find it obvious to combine the architecture of Budhia with the Toledo system to produce the predictable result of implementing path selection via multiplexers.
Claim 15,
Toledo discloses
A method of routing a packet in a network device, comprising:
generating, at first logic, first codes for the packet (para 0059- applies a simple hash to sum the 5-tuple of a packet header);
receiving, at the first logic from a memory, a second code that represents a number of paths through a network between the network device and a destination (para 0057- discloses using the total number of paths to determine a selected path);
performing, by first circuits, comparisons of the first codes with the second code and generate outputs in response to the comparisons, each of the outputs being a selection of one of the first codes or another code (para 0034- discloses a plurality of circuitry, para 0064- discloses ECMP routing scheme 490 depicts a simple hash function that sums the values of 5-tuple components (e.g., source port, destination port, source IP address, and destination IP address) and then applies the modulo operation to determine a number identifying a particular path, where the modulo is based on the number of available paths (here, 27, numbered from 0-26). Some of the possible paths are depicted in paths 495, including paths 410 and 426.);
Although Toledo discloses substantial limitations of the claim invention, it fails to explicitly disclose
selecting, by a second circuit, one of the outputs as a third code that represents one of the paths; and routing, by a packet processor, the packet based on the third code.
In an analogous art, Budhia discloses
selecting, by a second circuit, one of the outputs as a third code that represents one of the paths; and routing, by a packet processor, the packet based on the third code (col 28, lines 20-30- circuitry, fig. 3B, col 24, lines 13-24- discloses selecting an output of a plurality of algorithms to determine a selected path) .
One of ordinary skill in the art before the effective filing date of the invention would find it obvious to combine the path selection of Budhia with the Toledo system to produce the predictable result of selecting a path from a plurality based on performance.
Claim 16,
wherein the step of generating comprises: receiving, as input to second logic, at least a portion of the packet; and generating, by the second logic, the first codes as a hash of the input. (Toledo para 0059)
Claim 17,
wherein each of the first circuits includes a comparator, and wherein the step of performing comprises: performing, at the comparator of each of the first circuits, one of the comparisons and generate an output as a result. (para 0034- discloses a plurality of circuitry, para 0064- discloses ECMP routing scheme 490 depicts a simple hash function that sums the values of 5-tuple components (e.g., source port, destination port, source IP address, and destination IP address) and then applies the modulo operation to determine a number identifying a particular path, where the modulo is based on the number of available paths (here, 27, numbered from 0-26). Some of the possible paths are depicted in paths 495, including paths 410 and 426.)
Claim 18,
wherein each of the first circuits includes a multiplexer, and wherein the step of performing comprises: performing, by the multiplexer of each of the first circuits, a selection based on the output of the comparator to generate a respective one of the outputs. (Toledo para 0059- discloses logic to perform a selection of a path, Budhia col 28, lines 27-31- disclose implementing path selection through multiplexers and logic gates.)
One of ordinary skill in the art before the effective filing date of the invention would find it obvious to combine the architecture of Budhia with the Toledo system to produce the predictable result of implementing path selection via multiplexers.
Allowable Subject Matter
Claims 3-7, 11-12, 14 and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Relevant Prior Art:
Anubolu et al. U.S. Patent Application publication 11,095,552- discloses a method to select a path based on the number of paths, a threshold and routing index.
Hsu et al. U.S. Patent Application publication 8,149,839- discloses a method to determine path selection based on a ECMP algorithm and a rotating index.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH M COUSINS whose telephone number is (571)270-7746. The examiner can normally be reached 9:00am -5:00pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tonia Dollinger can be reached at (571) 272-4170. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JMC/Examiner, Art Unit 2459
/TONIA L DOLLINGER/Supervisory Patent Examiner, Art Unit 2459