Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see Response to Prior Art Rejection, filed March 31, 2026, with respect to the rejections of claims 1 – 20 under 35 U.S.C. 102 and 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new grounds of rejection is made in view of new art found in a search of prior art prompted by new limitations introduced by amendments.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 3, 5 – 7, 9 – 13, 15 – 17, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over McKean (cited in previous action) over Liu et al. (US Patent Application Publication 2005/0005062), hereinafter Liu.
Regarding claim 1, McKean teaches a storage system, comprising:
a first controller and a second controller (Fig. 1, Storage Controllers A and B), wherein the first controller and second controller separately communicate with at least one memory (Fig. 1, storage devices 114) via a shared interface device (The remaining components of the storage system 104 in Fig. 1 comprise the shared interface), wherein the shared interface device is a disk enclosure (Fig. 1, the storage system 104 as a whole; Column 3 lines 21 – 48, the storage system may be a single computing system), the disk enclosure includes a processor (Column 3 line 35), a cache (Fig. 1, discrete caches 122), and a hard disk mounting mechanism (Column 4 lines 41 – 62, the backplane 116 is in communication with storage devices 114, which may include hard disk drives), wherein the at least one memory is disposed behind the hard disk mounting mechanism of the disk enclosure, and is in communication with the processor of the disk enclosure (Fig. 1, the storage devices are mounted on the opposite side of the rest of the system from the backplane, and communicate with the storage controllers via the backplane);
the first controller is configured to send, to the shared interface device, a write instruction instructing the shared interface device to write first data (Fig. 4; The controller writes to the caches; Column 7 lines 6 – 34, the host’s command is forwarded to the interface/cache, that is, sent from the controller to the interface/cache);
the processor of the shared interface is configured to temporarily store the first data in the cache of the shared interface device (Fig. 4), and asynchronously write the first data temporarily stored in the cache into a first memory in the at least one memory (Column 8 lines 12 – 24, the discrete caches may be flushed to write to storage devices, this is asynchronous as it can happen at any time);
the second controller is configured to send a read instruction to the shared interface device after the first controller is faulty, wherein the read instruction instructs the shared interface device to query for second data, and the second data is all or a part of the first data (Column 8 lines 25 – 32, after failure of the first controller, the second controller assumes control to serve transactions, including using the first controller’s part of the cache);
the processor of shared interface device is further configured to obtain, according to the read instruction, all or part of the second data from the cache of the shared interface device, and provide all or the part of the second data to the second controller (Column 8 lines 25 – 32, data is retrieved from the first controller’s part of the cache); and
wherein the first controller is an active controller of the shared interface device and the second controller is a standby controller of the shared interface device (Column 6 lines 21 – 40, during normal operation, each controller operates its respective partition. In the event of a failure, the other partition takes over. One such partition may be designated the primary, and the other a designated mirror. That is, the controller operating the primary partition is the active controller, and the other controller is the standby controller).
McKean does not explicitly teach the system wherein in a normal working state, a first port of the shared interface device connected to the first controller is in an active state and a second port of the shared interface device connected to the second controller is in an inactive state, so that the shared interface device is configured to be invoked by the first controller and is not configured to be invoked by the second controller; and wherein after the first controller is faulty, the second port of the shared interface device is configured to enter the active state and start to be invoked by the second controller to receive the read instruction (McKean is directed to the function of the caches, and not the storage devices. It therefore does not describe what happens to the ports connecting to the storage devices).
Liu teaches an active/standby configuration for storage controllers (Abstract, paragraph 0014, paragraph 0075) wherein in a normal working state, a first port of the shared interface device connected to the first controller is in an active state and a second port of the shared interface device connected to the second controller is in an inactive state, so that the shared interface device is configured to be invoked by the first controller and is not configured to be invoked by the second controller (Paragraph 0075, one SVC/storage virtualization controller actively accesses the PSD/physical storage device while the other is in standby and its interconnect is disabled. These interconnects are SATA ports connected to the switching circuit which is part of an interface shared with the other controller as shown in Figs. 3, 4 and 6 and paragraph 0095); and wherein after the first controller is faulty, the second port of the shared interface device is configured to enter the active state and start to be invoked by the second controller to receive the read instruction (Paragraph 0119, when an SVC fails, an alternate SVC takes over in a switchover by rerouting the necessary signals; Paragraphs 0129 – 0132 teaches that this may be performed by disabling the malfunctioning port and enabling the other port. Figs. 40 and 41, which are truth tables for Fig. 4 and Fig. 5 respectively, also illustrate the enabling and disabling of ports).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention that the active/standby configuration described in McKean would be implemented in a manner similar to that described by Liu. One of ordinary skill in the art would, given McKean does not describe the behavior of the storage devices in detail, refer to other pieces of prior art to implement the ability for both controllers to access the storage devices. McKean describes a backplane, but does not describe how the backplane is implemented. It does, however, disclose the use of SATA for linking the host and the controllers (Column 3 line 61), and the controllers with the caches (Column 5 line 62). One of ordinary skill in the art would be drawn to consider the use of SATA for linking the storage and the controllers. Liu is furthermore structurally similar to McKean, where two controllers communicate with one another to confirm the other’s functioning (Liu paragraph 0015), and one takes over the other’s functions in case of a failure. Due to these similarities Liu would be a suitable piece of prior art for one of ordinary skill in the art implementing McKean to reference regarding details not explicitly disclosed in McKean. Furthermore, Liu teaches that active/standby configurations are commonly known in the art (Paragraph 0014), so Liu and McKean are part of a larger group of similar systems that are well-understood.
Regarding claim 2, McKean in view of Liu teaches the storage system according to claim 1, wherein the second controller is further configured to send, to the shared interface device, a write instruction instructing the shared interface device to write third data; and
the shared interface device is further configured to temporarily store the third data in the cache, and is further configured to asynchronously write the third data temporarily stored in the cache into the first memory (This operation is the same operation as that in claim 1, with different data and controller; McKean column 5 line 54 – column 6 line 40, each controller has associated partitions and perform reads and writes; McKean Fig. 4 shows that the controllers can write to the same cache).
Regarding claim 3, McKean in view of Liu teaches the storage system according to claim 2, wherein the cache comprises a first partition and a second partition, the first partition is used to temporarily store data for the first controller, the second partition is used to temporarily store data for the second controller (McKean Fig. 1, the caches are divided into partitions for each controller’s data), and a query range in which the shared interface device obtains all or the part of the second data in the cache comprises the first partition and the second partition (McKean column 6 lines 31 – 35, the partitions can be accessed by all controllers).
Regarding claim 5, McKean in view of Liu teaches the storage system according to claim 1, wherein the at least one memory further comprises a second memory (McKean Fig. 1, there are multiple storage devices 114, alternatively, controller caches 118), a memory access latency of the second memory is less than that of the first memory (McKean column 4 lines 41 – 54, the memories may contain a slower memory pool accessed infrequently; Alternatively, McKean column 4 line 63 – column 5 line 5, the controller cache is faster than the storage devices 114), and the shared interface device is further configured to:
synchronously back up the first data to the second memory after receiving the write instruction (McKean column 4 lines 26 – 40, the storage devices may be grouped together to provide redundancy for one another based on RAID; Alternatively, McKean column 5 lines 19 – 37, the storage controller stores a copy of data in its and/or a second controller’s controller cache over the interconnect before performing the write on the storage devices);
obtain, according to the read instruction, all or the part of the second data from the second memory based on the cache being abnormal, and provide all or part of the second data to the second controller (McKean Fig. 8, if the target data is not in the cache, target data is read from the storage device instead, and according to McKean Column 4 lines 41 – 54, the faster memories mapped to the second memories are used to service the cache; Alternatively, McKean Column 7 line 60 – Column 8 line 11, the controller caches act as redundant copies of the discrete caches).
Regarding claim 6, McKean in view of Liu teaches the storage system according to claim 1, wherein the storage system further comprises a third memory connected to the first controller (McKean Fig. 1; the other discrete caches and controller caches can constitute third memories relative to one of the discrete caches), and the first controller is further configured to:
back up the first data to the third memory (McKean Column 6 lines 35/36, data is mirrored across discrete caches; McKean Column 7 line 60 – Column 8 line 11, data is stored redundantly in the controller cache); and
forward, via the shared interface device, data backed up in the third memory to a fourth memory in the at least one memory based on the cache being abnormal (McKean Column 7 lines 6 – 34, if a discrete cache fails, a mirrored copy in one of the other discrete caches provides redundancy with respect to block 204 of McKean Fig. 2; McKean Column 7 line 60 – Column 8 line 11, if a discrete cache fails, the controller cache provides redundancy with respect to block 206 of McKean Fig. 2; In either case, block 210 of McKean Fig. 2 flushes at least one of the caches that have not failed, to a memory of the storage devices 114);
and the shared interface device is further configured to:
obtain, according to the read instruction, all or part of the second data from the fourth memory based on the cache being abnormal, and provide all or the part of the second data to the second controller (McKean Fig. 8, if the target data is not in the cache, target data is read from the storage device instead).
Regarding claim 7, McKean in view of Liu teaches the storage system according to claim 1, wherein the data comprises service data and/or metadata of the service data (The use cases described in Column 1 lines 15 – 59 constitute services), and the service data is data to be written as requested by a data write request received by the first controller (McKean Fig. 3, the first controller receives a request from a host).
Regarding claim 9, McKean in view of Liu teaches the storage system according to claim 1, wherein the shared interface device communicates with the first controller and/or the second controller by using a peripheral component interconnect express (PCIe) protocol (McKean Column 5 lines 54 – 66; Liu paragraph 0095, the controllers may connect to the switching circuit via a PCI-SATA converter).
Regarding claim 10, McKean in view of Liu teaches the storage system according to claim 1, wherein each of the at least one memory has only a single port for communication with the shared interface device (Liu Figs. 21, 22 and 35 depict configurations where each storage device only has a single port connection to the hub/switching circuit. Although Liu also teaches configurations where each memory is dual-ported, the switch allows for two controllers to access the same port on the storage device).
Regarding claim 11, McKean in view of Liu teaches a method (McKean Claims).
The method of claim 11 recites similar limitations to claim 1, and is similarly rejected.
Claim 12 recites similar language to claim 2, and is similarly rejected.
Claim 13 recites similar language to claim 3, and is similarly rejected.
Claim 15 recites similar language to claim 5, and is similarly rejected.
Claim 16 recites similar language to claim 6, and is similarly rejected.
Claim 17 recites similar language to claim 7, and is similarly rejected.
Claim 19 recites similar language to claim 9, and is similarly rejected.
Claim 20 recites similar language to claim 10 and is similarly rejected.
Claims 4 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over McKean in view of Liu, further in view of Lasker (cited in previous action).
Regarding claim 4, McKean in view of Liu teaches the storage system according to claim 3, wherein the shared interface device is further configured to:
temporarily store the first data in the first partition, and temporarily store the third data in the second partition (McKean Fig. 1, the caches are divided into partitions for each controller’s data); and
send the first data temporarily stored in the first partition and the third data temporarily stored in the second partition to the first memory (McKean Column 8 lines 19 – 24, the data is flushed from discrete caches to storage devices; McKean Column 8 lines 25 – 38, each controller may flush either partition).
McKean in view of Liu does not explicitly recite that the first and third data are sent consecutively (While there would necessarily be a sequence for flushing, it is not explicitly stated that the data write is consecutive).
Lasker teaches a memory controller in which data is sent to disks consecutively (Column 14, lines 41 – 53, writes to disks are performed in FIFO order).
It would be obvious to one of ordinary skill in the art before the effective filing date of the invention that, given that data is sent consecutively in Lasker, that the data in McKean in view of Liu could be sent consecutively. They would be motivated to do so because there are a finite number of ways the data could be flushed: either simultaneously or consecutively. In view of Lasker, it would be clear to one of ordinary skill in the art that either method would produce predictable results. It furthermore allows for multiple writes to the same region be consolidated to reduce traffic (Lasker column 14, lines 41 – 53).
Claim 14 recites similar limitations to claim 4, and is similarly rejected.
Claims 8 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over McKean in view of Liu, further in view of Parthasarathi (NPL, excerpt from Computer Architecture. Cited page is attributed to Dr A.P. Shanthi).
Regarding claim 8, McKean in view of Liu teaches the storage system according to claim 1, wherein a persistence address of each data stored in the shared interface device indicates a storage space (McKean Column 3 lines 1 – 8, McKean Column 7 lines 35 – 44).
McKean in view of Liu does not explicitly teach that, wherein for storage spaces that are adjacent to each other, data that correspond to the storage spaces are sent by the shared interface device consecutively according to a plurality of consecutive instructions, wherein the plurality of consecutive instructions do not apply to data stored in the shared interface device whose corresponding storage spaces are not adjacent to the storage spaces (McKean Column 6 lines 5 – 20 discusses SCM and a variety of storage technologies to provide faster latencies, but does not elaborate as to how).
Parthasarathi teaches that, for caches, for storage spaces that are adjacent to each other, data that correspond to the storage spaces are sent consecutively according to a plurality of consecutive instructions, wherein the plurality of consecutive instructions do not apply to data stored in the shared interface device whose corresponding storage spaces are not adjacent to the storage spaces (Page 2, the spatial aspect of locality of reference suggests fetching several items that reside at adjacent addresses, and cache memory is designed to take advantage of this. It follows that this would not apply to data that is not adjacent).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention that the caches and other memories of McKean in view of Liu follow the principles of locality of reference as taught by Parthasarathi. According to Parthasarathi page 2, locality of reference is a fundamental property of computer programs that makes accessing contiguous data more efficient. One of ordinary skill in the art would understand such a property and its effect on speed, which is desirable as stated by McKean (Column 6 lines 5 – 20). Additionally, McKean notes that the fast memory devices are block-addressable (Column 6 lines 5 – 20). Blocks are used by Parthasarathi to refer to a set of contiguous address locations (Page 3). It would be clear to one of ordinary skill in the art that these are referring to the same principle of consecutive address locations being moved as a group with consecutive instructions, and that doing so improves the speed of data transfer.
Claim 18 recites similar language to claim 8, and is similarly rejected.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Anderson (NPL, NetApp 7-Mode Hardware Architecture Tutorial) teaches the behavior of ports in an active-standby configuration for NetApp. Although it has a strong motivation to combine with McKean, it is not relied upon for a lack of technical detail. Schnapp et al. (2006/0015692), Pang et al. (2006/0136688) and Huang et al. (2010/0211715) teach similar technical details for active-standby memory controllers.
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/B.P.H./Examiner, Art Unit 2114
/ASHISH THOMAS/Supervisory Patent Examiner, Art Unit 2114
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