DETAILED ACTION
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/31/2024 and 03/13/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 8-12, and 16-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Takaki US 20170262393.
Regarding claim 1, Takaki teaches an apparatus (see figure 1) comprising:
a processor core configured to execute machine code instructions over a plurality of clock cycles and to receive a hardware signal (CPU 20, see para 0009, The semiconductor device includes a processor, e.g., a CPU (central processing unit), running an RTOS (real time operating system)); and
a circuit coupled to the processor core, wherein the circuit includes a counter (time management unit 10 and second counter 12), wherein the circuit is configured to generate the hardware signal (see para 0066, the second counter 12 has, for example, a function of generating the interrupt signal to the CPU 20) and is further configured to:
change a value stored in the counter by either incrementing or decrementing the value according to a clock associated with the clock cycles (see para 0020, The RTC (real time counter) 13 transmits a clock signal necessary for the first counter 11 and the second counter 12);
receive a read operation, directed to the counter, from the processor core (see para 0039-0041, when receiving the return signal from the CPU 20… the return processing circuit 16 takes in a count value Z of the second counter 12, and transmits this count value Z to the CPU 20 e.g. reading the counter from the CPU);
in response to receiving the read operation, determine the value stored in the counter (see figure 4 step S21, see para 0041, the return processing circuit 16 takes in a count value Z of the second counter 12);
determine whether to change a state of the hardware signal based at least in part upon the value stored in the counter; and change the state of the hardware signal to a first state (see para 0066, the second counter 12 has, for example, a function of generating the interrupt signal to the CPU 20 when counting down to a predetermined count value (for example, the count “0”) e.g. changing the state of the interrupt signal).
Regarding claim 2, Takaki teaches the processor core is further configured to: stall in response to the state of the hardware signal being changed to the first state (see para 0071, when the interrupt signal is transmitted from the second counter 12, the MCU 1 starts the return process from the low power mode to the normal mode (Step S18) e.g. when the interrupt is not generated (first state), the CPU is configured to stall in the low power mode).
Regarding claim 3, Takaki further teaches the circuit is further configured to: change the state of the hardware signal to a second state in response to the value stored in the counter being changed to a specified value; and wherein the processor core is further configured to: resume execution of the machine code instructions in response to the second state of the hardware signal (see para 0081, when the count value becomes “0”, the second counter 12 transmits the interrupt signal to the CPU 20, also see para 0074, the CPU 20 returns to the normal mode due to the interrupt signal from the second counter 12 e.g. resuming execution of the CPU when interrupt signal is generated).
Regarding claim 8, Takaki further teaches the processor core is further configured to: populate a first register with a non-zero value during runtime, and wherein the counter is configured to decrement the non-zero value with each clock cycle (see para 0032, the CPU 20 stores the count value in an internal register, also see para 0066, The second counter 12 starts to count down from a predetermined counter value Z).
Regarding claim 9, Takaki further teaches the processor core is further configured to: populate a first register with a non-zero value during runtime, and wherein the counter is configured to increment from zero to the non-zero value with each clock cycle (see para 0047, the suspension processing circuit 15 causes the second counter 12 to count up).
Regarding claim 10, Takaki further teaches the circuit is further configured to: populate a second register with a first value stored in the counter corresponding to a time at which the read operation is received from the processor core (see para 0032, the suspension processing circuit 15 may instead store the count value X in the internal register of the suspension processing circuit 15 itself).
Regarding claim 11, Takaki further teaches a method (see figure 1 and figure 4) comprising:
initiating a counter (second counter 12);
receiving a read operation from a processor core, wherein the read operation is directed to the counter (see para 0030-0034, the CPU 20 transmits the suspension signal to the time management unit 10… the suspension processing circuit 15 causes the second counter 12 to start counting);
stalling the processor core, including causing a hardware signal to attain a first state, in response to the read operation from the processor core (see para 0071, when the interrupt signal is transmitted from the second counter 12, the MCU 1 starts the return process from the low power mode to the normal mode (Step S18) e.g. when the interrupt is not generated (first state), the CPU is configured to stall in the low power mode), wherein the hardware signal is transmitted on a bus from a hardware logic unit to the processor core (see figure 1, bus connecting time management unit 10 to the CPU 20);
holding the first state of the hardware signal during a time period in which the counter performs a counter operation (see para 0066, the second counter 12 starts to count down from a predetermined counter value Z under the control of the suspension processing circuit 15); and
causing the hardware signal to attain a second state, thereby un-stalling the processor core, in response to the counter reaching a specified value (see para 0066, the second counter 12 has, for example, a function of generating the interrupt signal to the CPU 20 when counting down to a predetermined count value (for example, the count “0”), also see para 0071, when the interrupt signal is transmitted from the second counter 12, the MCU 1 starts the return process from the low power mode to the normal mode (Step S18) e.g. resuming operation of the CPU 20 when the interrupt signal is generated (second state)).
Regarding claim 12, Takaki further teaches initiating the counter is performed in response to detecting an interrupt signal from a peripheral (see para 0075, the RTOS restarts normal operations in response to the interrupt signal from the external device 100).
Regarding claim 16, Takaki teaches an apparatus (see figure 1) comprising:
a hardware counter circuit, coupled to a first bus (second counter 12 and the bus of the time management unit 10 connecting to the second counter), wherein the first bus comprises a data bus configured to support read and write access to the hardware counter circuit from a processing unit (see para 0023, a process of reading the count value of the second counter 12); and
hardware logic coupled to the hardware counter circuit and to a second bus, wherein the second bus is coupled to the processing unit (time management unit coupled to CPU 20 via a second bus as shown in figure 1), further wherein the hardware logic is configured to assert and de-assert a hardware signal on the second bus in response to a value of the hardware counter circuit at a read operation on the first bus (see para 0066, the second counter 12 has, for example, a function of generating the interrupt signal to the CPU 20 when counting down to a predetermined count value (for example, the count “0”) e.g. assert/de-assert of the interrupt signal).
Regarding claim 17, Takaki further teaches the hardware logic further comprises: an interrupt signal input coupled to a peripheral bus (see figure 1, peripheral bus connected to external device 100, see para 0071, the interrupt signal is transmitted from the external device 100).
Regarding claim 18, Takaki further teaches a register configured to populate a value from the register to the hardware counter circuit to begin a counting operation (see para 0032, the CPU 20 stores the count value in an internal register, also see para 0066, The second counter 12 starts to count down from a predetermined counter value Z).
Regarding claim 19, Takaki further teaches populate the value from the register to the hardware counter circuit in response to receiving an interrupt at an interrupt input ((see para 0037, when the interrupt signal is input from the external device 100… starts the return process from the low power mode to the normal mode e.g. begin the counting operation of the return process).
Allowable Subject Matter
Claims 4-7, 13-15 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 4-7, and 13, the known prior arts fail to explicitly discloses “reading a register associated with the peripheral subsequent to the hardware signal attaining the second state” in combination with other limitation found in the independent claims and any intervening claims.
Regarding claim 14, the known prior arts fail to explicitly discloses “initiating the counter includes receiving a write operation from the processor core during runtime, wherein the write operation is configured to store a non-zero value to the counter, wherein the non-zero value corresponds to a quantity of clock cycles of the processor core associated with the specified value” in combination with other limitation found in the independent claim.
Regarding claim 15, the known prior arts fail to explicitly discloses “storing a value of the counter corresponding to a time at which the read operation is received, including replacing a previously stored value of the counter in response to the value of the counter being greater than the previously stored value or in response to the value of the counter being lesser than the previously stored value” in combination with other limitation found in the independent claim.
Regarding claim 20, the known prior arts fail to explicitly discloses “a third bus, coupling the register to the processing unit, the third bus configured for read and write access of the register during runtime, including a write operation from the processing unit of a non-zero value corresponding to a quantity of clock cycles of the processing unit associated with the value” in combination with other limitation found in the independent claim and the intervening claim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Tran US 20230244489 discloses a processor includes a time counter to specify when the instructions may be provided to an execution pipeline
Heller et al US 20130111092 discloses a timer/counter associate with an interrupt controller to schedule a timer interrupt for a processor
Sohm et al US 20070005842 discloses systems and methods for stall monitoring
Inomata et al US 20010027533 discloses a timer to mask/unmask a wait signal to a processor
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/PHONG H DANG/Primary Examiner, Art Unit 2184