DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, “a plurality of regional clock signals… for a clock region”, “a plurality of neighboring clock signals… for clocking neighboring regions”, “a plurality of global clock signals… for clocking logic blocks…”: indefinite because each of these may be interpreted as an intended use for the clock signals, and therefore possible non-limiting. It is unclear how the device is configured to use the clocks after they have been generated because their use is not explicitly recited. The Examiner recommends amending the claims to more clearly recite whether the clocks are used by the various regions, e.g., “a plurality of regional clock signals… each clock region coupled to one of the plurality of RCSs”.
Claim 2,
“…a plurality of secondary clock signals… generated from the plurality of RCSs with a second CSQ”: it is unclear whether the second CSQ is associated with the plurality of SCSs or the plurality of RCSs. The Examiner notes that claim 1 recites a plurality of RCSs without clearly specifying that they have the first CSQ of the “clock source”.
“…for clocking logic blocks with less time-sensitive logic operations”: indefinite because the claims provide no frame of reference for determining whether operations are less time-sensitive (i.e., the claim does not recite other operations that are more time-sensitive in comparison). Additionally, this language may be interpreted as a statement of intended use (unclear whether the less time-sensitive logic operations are actually present in the invention), and therefore possibly non-limiting.
Claim 3,
“…the plurality of SCSs with the second CSQ”: lack of proper antecedent basis, parent claim 1 does not recite a plurality of SCSs with a second CSQ.
“less time-time sensitive logic operations”: indefinite on the same basis as claim 2.
Claim 5,
“…clock output of PLL”: missing article, unclear whether this references previously recited PLL of claim 4.
“…the output of the clock source is programmable selected as an RCS to clock logic block in a designated region”: indefinite because this language is unclear and requires revision.
Claim 6, “the plurality of SCSs”: lack of proper antecedent basis because claims 1 and 4 do not recite a plurality of SCSs with a second CSQ.
Claim 8, “…the output of the clock source is programmable selected as an RCS to clock logic block in a designated region”: indefinite on the same basis as claim 5.
Claim 9,
“identifying a clock source of FPGA…”: missing article, unclear whether this references previously recited FPGA of line 1. Claims 10, 11, and 13-15 employ the same language and are similarly indefinite.
“…for clock distributions with various configurable clock speeds”: indefinite because it may be interpreted as a statement of intended use and possibly non-limiting.
“…for providing first high-speed clock signals with relatively low clock skew”: indefinite because “relatively low” is unclear/undefined, and because claim language may be interpreted as a statement of intended use or an intended result (and possibly non-limiting). Similar reasoning may be applied to “…for providing second high-speed clock signals…”
“the device” (last line): lack of proper antecedent basis.
Claim 12, “the first regional clock signals”, “the second regional clock signals”: lack of proper antecedent basis because claim 9 does not identify a first regional clock signal and a second regional clock signal.
Claim 13, “the first quadrant of FGPA”: lack of proper antecedent basis because claim 9 does not identify a first quadrant.
Claim 14, “the second quadrant”: indefinite on the same basis as claim 13.
Claim 15, “four quadrants of FPGA”: missing article, unclear whether this references previously recited quadrants of claim 9.
Claim 16, “one or more clock sources”: indefinite because claim 9 recites a clock source, unclear whether the one or more clock sources encompasses the original clock source of claim 9.
Claim 19,
“a plurality of regional clock signals… for a clock region”, “a plurality of neighboring clock signals… for clocking neighboring regions”, “a plurality of second clock signals… for clocking logic blocks…”: indefinite because each of these may be interpreted as an intended use for the clock signals, and therefore possible non-limiting. It is unclear whether the device is configured to use the clocks after they have been generated.
“a plurality of secondary clock signals.... generated from the plurality of RCSs with a second CSQ”: unclear whether the second CSQ is associated with the secondary clock signals or the plurality of RCSs.
“less time-sensitive logic operations”: indefinite on the same basis as claim 2.
Claim 20, “a plurality of global clock signals… for clocking logic blocks…”: indefinite because each of these may be interpreted as an intended use for the clock signals, and therefore possible non-limiting. It is unclear whether the device is configured to use the clocks after they have been generated.
Claim 21,
“…the plurality of SCSs with the second CSQ”: lack of proper antecedent basis.
“…for clocking less time-sensitive logic operations…”: see claim 2.
“the four (4) quadrants of the device”: lack of proper antecedent basis because claim 19 does not identify quadrants.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-8 and 19-22 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-8 and 13 of U.S. Patent No. 11,216,022. Although the claims at issue are not identical, they are not patentably distinct from each other because the application claims are anticipated by, or obvious variants of, the patent claims.
While the application claims are not identical to the patent claims, they recite the same limitations when the claims are considered collectively, thereby representing an obvious variant. For example, the limitations of application claim 1 are recited in patent claims 1 and 2, while the limitations of application claim 2 are recited in patent claim 1.
Application claims 3-8 are anticipated by patent claims 3-8, respectively, because they recite the same limitations.
Application claims 19-22 are anticipated by patent claims 1-4 because they collectively recite the same limitations.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4, 9, 12, and 19-22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Teh et al., U.S. Patent No. 9,971,733.
Regarding claim 1, Teh discloses a device comprising:
a plurality of regional clock signals (“RCSs”) [Fig. 5A: clock tree 521] generated from a clock source [PLL 500] with a first clock signal quality (“CSQ”) [col. 7, lines 1-5: PLL frequency] for a clock region [intended use, non-limiting];
a plurality of neighboring clock signals (“NCSs”) [clock tree 525] generated from a neighboring clock source [DLL 524] with the first CSQ [col. 7, lines 35-52: DLL only performs phase adjustment, implying clock tree 525 has the same frequency as clock tree 525] for clocking neighboring regions [intended use, non-limiting]; and
a plurality of global clock signals (“GCSs”) [Clk3, Clk4] generated from the clock source with the first CSQ [PLL 500] for clocking logic blocks in four (4) quadrants of the device [intended use, non-limiting].
Regarding claim 4, Teh discloses one of the plurality of RCSs is generated in response to a clock output of phase lock loop (“PLL”) and an output of the clock source [PLL 500].
Regarding claim 9, Teh discloses a method comprising:
identifying a clock source [PLL 500] of an FGPA [col. 3, lines 40-51: “Main IC die 104 may be… a programmable logic device (PLD)… Examples of programmable logic devices include… field programmable logic arrays (FPGAs)…”] for clock distribution with various configurable clock speeds [intended use, non-limiting];
generating a plurality of regional clock signals (“RCSs”) [clock tree 521] based on the clock source [PLL 500] for providing first high-speed clock signals with relatively low clock skew [intended use, non-limiting];
generating a plurality of neighboring clock signals (“NCSs”) [clock tree 525] in accordance with the clock source [PLL 500] for providing second high-speed clock signals for clocking neighboring regions [intended use, non-limiting]; and
providing a plurality of global clock signals (“GCSs”) [Clk3, Clk4] based on the clock source [PLL 500] for clocking logic blocks in four (4) quadrants of the device [intended use, non-limiting].
Regarding claim 12, Teh discloses providing a clock fabric capable of generating a first unique clock frequency for the first regional clock signals and a second unique clock frequency for the second regional clock signals [col. 7, lines 1-5, clock tree from second PLL: “… UIB 110 may be provided with two or more integer or fractional phase-locked loops (PLL) running at… different frequencies to independently serve as clock sources for each quadrant or quadrant pair.”].
Claims 19-22 are rejected on the same basis as claims 1-4.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Jacobowitz et al., U.S. Patent Application Publication No. 2008/0256382, discloses a system for generating a plurality of core clock signals based on a system clock that is distributed among a plurality of chips [Fig. 1, 2].
Magoshi, U.S. Patent Application Publication No. 2002/0167857, discloses a system for generating a plurality of clocks based on a source clock that is hierarchically distributed through a plurality of regions [Fig. 2].
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JI H BAE whose telephone number is (571)272-7181. The examiner can normally be reached Tuesday to Friday and every other Monday, 9 am to 6 pm.
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/JI H BAE/Primary Examiner, Art Unit 2176 U.S. Patent and Trademark Office
Phone: 571-272-7181
Fax: 571-273-7181
ji.bae@uspto.gov