Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
1. This action is responsive to communication filed on: 26 January 2026 with acknowledgement of an original application filed on 31 May 2024 and that this application is a continuation of a provisional application filed on 12 December 2023.
2. Claims 1-20 are pending. Claims 1, 14, and 20, are independent claims. Claims 1, 14, and 20, have been amended.
Response to Arguments
3. Applicant's arguments filed 26 January 2026 have been fully considered however they moot to due the new grounds of rejection below do to claim amendments.
Claim Rejections - 35 USC § 112
4. The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
5. Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The independent claims have been amended to include the limitation “a hashing circuit in memory”. Support for such a limitation is not supported by the Applicant’s disclosure. The Examiner notes as is well known in the art a hashing circuit, is performing an operation, a memory does not perform operations on data. As explained in the Applicant’s disclosure see Figure 4, as well as paragraphs 11, 15, 49, the hashing circuit is connected to memory. The Applicant’s disclosure also states, the hashing circuit is part of a Serial Peripheral Interface memory module or is part of a single semiconductor chip. Appropriate Correction is required.
6. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
7. Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The Applicant’s representative has amended the independent claims so that the independent claims state:
“A method, comprising: calculating, by a hash circuit in a memory, a hash value based on a received data set, the received data set being included in one or more received memory write commands, wherein the system verifies the received data set using the hash value.”
The Examiner considers these independent claims indefinite because the limitations do make sense for (i.e. indefinite) for a variety of reasons.
One – a memory that contains a hashing circuit is not a memory. A memory does not perform operations on data. According to Applicant’s discloser Fig. 4, item 405, “a hashing circuit is connected to a memory”.
Two – what data is being verified, if a hash value is calculated based on received data what is the hash value being compared to? According to Applicant’s disclosure paragraph 43, which is shown below:
In some embodiments, therefore hash values are used to verify error-free-reception of the data by the RAMs 110. Referring again to FIG. 1B, each of the RAMs 110 may include one or more registers 320 (FIG. 3; e.g., one or more 8-bit registers, which may be referred to as hash value registers) for storing a hash value (several registers may be used if the hash value is too long to fit in one register). When the RAM 110 is being programmed, all of the data it receives (which may be referred to as a received data set, the received data set corresponding to (and, in the absence of errors, being equal to) a transmitted data set transmitted by the baseboard management controller) may be hashed into a single hash value, e.g., by a hashing circuit 120 (FIG. 1B; the hashing circuit 120 is shown in only one of the RAMs 110; in some embodiments, a hashing circuit 120 may be present in several or all of the RAMs 110). The baseboard management controller 115 may also calculate a hash value, which may be referred to as a comparison value, using the transmitted data and the same hashing algorithm. The baseboard management controller 115 may then, after programming the RAMs 110, read the hashed values, and compare them to the respective comparison values (or to the comparison value, if the comparison values for all of the RAMs 110 are the same) and, for each such comparison conclude that (i) if the hash value read from the hash value registers of the RAM 110 matches the comparison value, the data was written without errors, or (ii) if the hash value read from the hash value registers of the RAM 110 does not match the comparison value the data was not written without errors. If the data was not written without errors, the baseboard management controller 115 may perform additional testing or troubleshooting and (either immediately or after performing additional testing or troubleshooting) report the fault to a higher-level management system (e.g., to a host that is connected to the computing system, or to a human operator (e.g., via a display, or via an automated email report, or via an automated short message system (SMS) report)). A computing system that exhibits such a fault may (either immediately, or after further testing) be taken out of service and scrapped.
Taken into account this paragraph 43 as well as Figure 4, it is suggested the independent claims be amended as indicated below. The Examiner notes these amendments are only to overcome the 112 rejection, the prior art rejection below teaches these limitations as well as the presented claims.
[Examiner’s Amendment to overcome 112 rejection] A method, comprising: calculating, by a hash circuit [[in]] connected to a memory, a hash value based on a received data set, store the hash value in one or more memory-mapped locations; send the received data set to the baseboard management controller memory module to form a transmitted data set using calculate a comparison hash value based on the transmitted data set; and wherein the system verifies the received data set matches the transmitted data set using the stored and calculated hash values [[value]].”
Appropriate Correction required.
Claim Rejections – 35 USC § 103
8. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
9. Claims 1, 4, 7, 11, 13-14, 17, and 20, are rejected under 35 U.S.C. 103 as being unpatentable over Flynn et al. U.S. Patent Application Publication No. 2012/0203980 (hereinafter ‘980) in view of Ghosh et al. U.S. Patent Application Publication No. 2018/0183573 (hereinafter ‘573).
As to independent claim 14, “A method, comprising:” and “the received data set being included in one or more received memory write commands, wherein the system verifies the received data set using the hash value” is taught in ‘980 Abstract, paragraphs 14-15, 20, and 50, note “the hash check module is located on the data storage device and the data storage device utilizes the hash check module to validate a read data packet by comparing the received hash value with the stored hash value retrieved from the data storage device” as well as “a module may be implemented as a hardware circuit”;the following is not explicitly taught in ‘980:
“calculating, by a hashing circuit in a memory, a hash value based on a received data set” however ‘573 teaches a direct memory access (DMA) controller circuit to read and write data directly to and from memory circuits and perform on-the-fly hashing circuit to hash data received or read from a first memory circuit that perform integrity check protection before writing data to a second memory circuit in the Abstract and paragraph 13.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention of an apparatus, system, and method for validating that correct data is read from a data storage device taught in ‘089 to include a means to perform hashing directly to and from memory circuits. One of ordinary skill in the art would have been motivated to perform such a modification support data integrity while improving performance with less computational complexity see ‘573 paragraph 12.
As to dependent claim 17, “The method of claim 15, wherein the memory-mapped locations are one or more memory locations in the memory” is taught in ‘980 paragraphs 67.
As to independent claim 20, “A system, comprising: a memory” and “the received data set being included in one or more received memory write commands, and wherein the system verifies the received data set using the hash value” is taught in ‘980 Abstract, paragraphs 14-15, 20, and 50, note “the hash check module is located on the data storage device and the data storage device utilizes the hash check module to validate a read data packet by comparing the received hash value with the stored hash value retrieved from the data storage device” as well as “a module may be implemented as a hardware circuit”;
the following is not explicitly taught in ‘980:
“and a means for hashing in the memory, wherein the means for hashing is configured to calculate a hash value based on a received data set” however ‘573 teaches a direct memory access (DMA) controller circuit to read and write data directly to and from memory circuits and perform on-the-fly hashing circuit to hash data received or read from a first memory circuit that perform integrity check protection before writing data to a second memory circuit in the Abstract and paragraph 13.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention of an apparatus, system, and method for validating that correct data is read from a data storage device taught in ‘089 to include a means to perform hashing directly to and from memory circuits. One of ordinary skill in the art would have been motivated to perform such a modification support data integrity while improving performance with less computational complexity see ‘573 paragraph 12.
As to independent claim 1, this claim is directed to a system executing the method of claim 14; therefore, it is rejected along similar rationale.
As to dependent claim 4, this claim contains substantially similar subject matter as claim 17; therefore, it is rejected along similar rationale.
As to dependent claim 7, “The system of claim 2, comprising a Serial Peripheral Interface memory module comprising the memory and the hashing circuit” is taught in ‘980 paragraph 61.
As to dependent claim 11, “The system of claim 1, wherein the memory and the hashing circuit are part of a single semiconductor chip” is shown in ‘980 paragraphs 50 and 52.
As to dependent claim 13, “The system of claim 1, wherein the received data set includes an address for each write operation and a value for each write operation” is disclosed in ‘980 Abstract, paragraphs 14, 20, and 23.
10. Claims 2-3, 5, 15-16, and 18, are rejected under 35 U.S.C. 103 as being unpatentable over Flynn et al. U.S. Patent Application Publication No. 2012/0203980 (hereinafter ‘980) in view of Ghosh et al. U.S. Patent Application Publication No. 2018/0183573 (hereinafter ‘573) in further view of Fujiwara U.S. Patent Application Publication No. 2010/0312986 (hereinafter ‘986).
As to dependent claim 15, the following is not explicitly taught in ‘980 and ‘573: “The method of claim 14, further comprising storing the hash value in one or more memory-mapped locations” however ‘986 teaches the address of the hash value is registered in a memory map in paragraphs 25-26.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention of an apparatus, system, and method for validating that correct data is read from a data storage device taught in ‘980 and ‘573 to include a means to map the hash value to the memory location. One of ordinary skill in the art would have been motivated to perform such a modification to detect a data transmission error see ‘986 paragraphs 3-4.
As to dependent claim 16, “The method of claim 15, wherein the memory-mapped locations are one or more memory-mapped registers in the hashing circuit” is taught 986 Abstract, note a semiconductor integrated circuit includes registers.
As to dependent claim 18, “The method of claim 15, wherein the hash value is further based on an initial value stored in the one or more memory-mapped locations” is shown in ‘986 Abstract and paragraph 5, note “first data” is interpreted equivalent to “initial value”.
As to dependent claims 2-3 and 5, these claims contain substantially similar subject matter as claims 15-16 and 18; therefore, they are rejected along similar rationale.
11. Claims 6, 8-9, and 19, are rejected under 35 U.S.C. 103 as being unpatentable over Flynn et al. U.S. Patent Application Publication No. 2012/0203980 (hereinafter ‘980) in view of Ghosh et al. U.S. Patent Application Publication No. 2018/0183573 (hereinafter ‘573) in further view of Wright et al. U.S. Patent Application Publication No. 2020/0342109 (hereinafter ‘109).
As to dependent claim 19, the following is not explicitly taught in ‘980 and ‘573: “The method of claim 18, wherein the one or more memory-mapped locations are externally read-only” however ‘109 teaches the memory locations can be “read-only” in paragraph 57.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention of an apparatus, system, and method for validating that correct data is read from a data storage device taught in ‘980 and ‘573 to include a means to utilize read-only memory. One of ordinary skill in the art would have been motivated to perform such a modification to provide a secure computer isolated from unsecure networks see ‘109 paragraph 1.
As to dependent claim 6, this claim contains substantially similar subject matter as claim 19; therefore, it is rejected along similar rationale.
As to dependent claim 8, “The system of claim 7 comprising: a printed circuit board; a baseboard management controller on the printed circuit board; and a plurality of Serial Peripheral Interface memory modules, comprising the Serial Peripheral Interface memory module, on the printed circuit board” is taught in ‘109 Abstract and paragraphs 20-24 and 29;
“wherein the baseboard management controller is configured: to send the one or more write commands, including a transmitted data set, to the Serial Peripheral Interface memory module” is shown in ‘109 paragraphs 29-31;
“to calculate a comparison value based on the transmitted data set, to read the hash value from the one or more memory-mapped locations, and to compare the hash value and the comparison value” is disclosed in ‘109 paragraph 47.
As to dependent claim 9, “The system of claim 8, wherein: the baseboard management controller is further configured: to read an initial value from the one or more memory-mapped locations before sending the one or more write commands; and to calculate a comparison value further based on the initial value” is taught in ‘109 paragraphs 47 and 66.
12. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Flynn et al. U.S. Patent Application Publication No. 2012/0203980 (hereinafter ‘980) in view of Ghosh et al. U.S. Patent Application Publication No. 2018/0183573 (hereinafter ‘573) in further view of Wright et al. U.S. Patent Application Publication No. 2020/0342109 (hereinafter ‘109) in further view of Caci U.S. Patent Application Publication No. 2012/0131673 (hereinafter ‘673).
As to dependent claim 10, the following is not explicitly taught in ‘980, ‘573, and ‘109: “The system of claim 8, further comprising a plurality of computing circuits on the printed circuit board, each computing circuit being: connected to a respective Serial Peripheral Interface memory module of the Serial Peripheral Interface memory modules, and configured to read instructions from the respective Serial Peripheral Interface memory module” however ‘673 teaches a system for protecting a circuit board such as a printed circuit board (PCB) from tampering as well as computing a hash code based on the state of memory in paragraphs 6-8.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention of an apparatus, system, and method for validating that correct data is read from a data storage device taught in ‘980, ‘573, and ‘109 to include a means to verify circuit on the printed circuit board. One of ordinary skill in the art would have been motivated to perform such a modification to protect the intellectual property contained within any given circuit board see ‘673 paragraphs 1-5.
13. Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Flynn et al. U.S. Patent Application Publication No. 2012/0203980 (hereinafter ‘980) in view of Ghosh et al. U.S. Patent Application Publication No. 2018/0183573 (hereinafter ‘573) in further view of Piccirillo et al. U.S. Patent Application Publication No. 2011/0219150 (hereinafter ‘150).
As to dependent claim 12, the following is not explicitly taught in ‘980 and ‘573: “The system of claim 1, wherein the hashing circuit comprises a linear feedback shift register” however ‘150 teaches using a linear feedback shift register to calculate a hash and data manipulation in the Abstract and paragraphs 18, 23, and 38.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention of an apparatus, system, and method for validating that correct data is read from a data storage device taught in ‘980 and ‘573 to include a means to utilize a linear feedback shift register. One of ordinary skill in the art would have been motivated to perform such a modification because Direct Memory Access (DMA) is an essential feature of modern computers as computer system become more sophisticated additional data manipulation operations are expected methods are needed to avoid delays see ‘150 paragraphs 18-19.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
14. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELLEN C TRAN whose telephone number is (571) 272-3842. The examiner can normally be reached Monday-Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Pwu can be reached at 571-272-6798. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/ELLEN TRAN/Primary Examiner, Art Unit 2433 20 March 2026