DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. This action is in response to application filed on June 1, 2024.
Information Disclosure Statement
3. The information disclosure statement (IDS) submitted on 6/1/2024 have been considered by the examiner.
Drawings
4. The drawings were received on June 24, 2024. These drawings are accepted.
Claim Objections
5. Claims 3 and 5 are objected to because of the following informalities:
On line 3 of claim 3, “pair of diodes switches” should be replaced with --pair of diodes--. In other words, “switches” should be removed.
On line 2 of claim 5, “didoes” should be changed to --diodes--.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
6. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
7. Claims 1, 3, 9, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Perreault et al (WO-2020252250-A2).
Regarding claim 1, Perreault et al discloses a power converter (i.e. circuit of Figure 9) comprising:
a first stage (Fig. 9, circuit of capacitor 910c and transistors S1 and S2) having a first terminal (Fig. 9, drain terminal of transistor S1) electrically connected to an input (Fig. 2, terminal carrying current iin) of the power converter (i.e. circuit of Figure 9) and a second terminal (Fig. 9, source terminal of transistor S2) electrically connected to a first output (Fig. 9, terminal carrying current iout) of the power converter (i.e. circuit of Figure 9);
a second stage (Fig. 9, circuit of diodes 908a and 908b) having a first terminal (Fig. 9, cathode of diode 908a) electrically connected to the first output (Fig. 9, terminal carrying current iout) of the power converter (i.e. circuit of Figure 9) and a second terminal (Fig. 9, anode of diode 908b) electrically connected to a second output (Fig. 9, negative terminal of element 952) of the power converter (i.e. circuit of Figure 9); and
a piezoelectric-resonator (Fig. 9, piezoelectric resonator 902) having a first terminal (Fig. 9, terminal from piezoelectric resonator 902 connecting to shared node between transistors S1 and S2) electrically connected to a third terminal (Fig. 9, shared node between transistors S1 and S2) of the first stage (Fig. 9, circuit of capacitor 910c and transistors S1 and S2) and a second terminal (Fig. 9, terminal from piezoelectric resonator 902 connecting to shared node between diodes 908a and 908b) electrically connected to a third terminal (Fig. 9, shared node between diodes 908a and 908b) of the second stage (Fig. 9, circuit of diodes 908a and 908b),
wherein at least one of the first stage (Fig. 9, circuit of capacitor 910c and transistors S1 and S2) or the second stage comprises a switched capacitor circuit (Fig. 9, circuit of capacitor 910c and transistors S1 and S2) including a plurality of semiconductor switches (Fig. 9, transistors S1 and S2) and at least one flying capacitor (Fig. 9, capacitor 910c).
Regarding claim 3, Perreault et al further discloses wherein the first stage (Fig. 9, circuit of capacitor 910c and transistors S1 and S2) comprises the switched capacitor circuit (Fig. 9, circuit of capacitor 910c and transistors S1 and S2) and the second stage (Fig. 9, circuit of diodes 908a and 908b) comprises a pair of diodes (i.e. diodes 908a and 908b), and wherein the third terminal (Fig. 9, shared node between diodes 908a and 908b) of the second stage (Fig. 9, circuit of diodes 908a and 908b) is located between the pair of diodes (i.e. diodes 908a and 908b) of the second stage (Fig. 9, circuit of diodes 908a and 908b).
Regarding claim 9, Perreault et al further discloses a control circuit (i.e. controller for switches 904a and 904b) (See ¶[0035] and [0037]) electrically connected to each semiconductor switch (Fig. 9, transistors S1 and S2) and configured to control operation of the semiconductor switches (Fig. 9, transistors S1 and S2) in a plurality of operation modes.
Regarding claim 19, Perreault et al discloses a method for controlling operation of a power converter (i.e. circuit of Figure 9) including a first stage (Fig. 9, circuit of capacitor 910c and transistors S1 and S2), a second stage (Fig. 9, circuit of diodes 908a and 908b) and a piezoelectric-resonator (Fig. 9, piezoelectric resonator 902), wherein the first stage (Fig. 9, circuit of capacitor 910c and transistors S1 and S2) includes a plurality of semiconductor switches (Fig. 9, transistors S1 and S2) and at least one flying capacitor (Fig. 9, capacitor 910c), the method comprising:
generating, by a controller (i.e. controller for switches 904a and 904b) (See ¶[0035] and [0037]) of the power converter (i.e. circuit of Figure 9), switching signals (Fig. 9, signals at gate terminals of switches 904a and 904b) at a fixed switching frequency;
supplying, by the controller (i.e. controller for switches 904a and 904b), the switching signals (i.e. controller for switches 904a and 904b) to at the first stage (Fig. 9, circuit of capacitor 910c and transistors S1 and S2); and
operating, by the first stage (Fig. 9, circuit of capacitor 910c and transistors S1 and S2), the plurality semiconductor switches (Fig. 9, transistors S1 and S2) at the fixed switching frequency.
Claim Rejections - 35 USC § 103
8. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
9. Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Perreault et al (WO-2020252250-A2) in view of Xia et al (US 2021/0399638).
Regarding claim 2, Perreault et al discloses wherein the first stage (Fig. 9, circuit of capacitor 910c and transistors S1 and S2) comprises the switched capacitor circuit (Fig. 9, circuit of capacitor 910c and transistors S1 and S2) and the second stage (Fig. 9, circuit of diodes 908a and 908b) comprises a pair of diodes (i.e. diodes 908a and 908b), and wherein the third terminal (Fig. 9, shared node between diodes 908a and 908b) of the second stage (Fig. 9, circuit of diodes 908a and 908b) is located between the pair of diodes (i.e. diodes 908a and 908b) of the second stage (Fig. 9, circuit of diodes 908a and 908b).
Perreault et al fails to explicitly disclose where the pair of diodes are a pair of semiconductor switches.
Xia et al discloses where a pair of diodes (Fig. 2, diodes 224 and 228) can be a pair of semiconductor switches (Fig. switches 524 and 528) (See ¶[0073]-[0075]).
Therefore, it would have been obvious, to one have ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the circuit of Perreault et al, by replacing the pair of diodes with a pair of semiconductors, as taught by Xia et al, in order to obtain a circuit with reduced conduction losses and increased efficiency.
Allowable Subject Matter
10. Claims 10-18 are allowed.
11. Claims 4-8 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
12. The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 4, the prior art fails to disclose or suggest the emboldened and italicized features below:
A power converter,
wherein the second stage comprises the switched capacitor circuit and the first stage comprises a pair of semiconductor switches, and wherein the third terminal of the first stage is located between the pair of semiconductor switches of the first stage.
Regarding claim 5, the prior art fails to disclose or suggest the emboldened and italicized features below:
A power converter,
wherein the second stage comprises the switched capacitor circuit and the first stage comprises a pair of didoes, and wherein the third terminal of the first stage is located between the pair of diodes of the first stage is located between the pair of diodes of the first stage.
Regarding claims 6-8, the prior art fails to disclose or suggest the emboldened and italicized features below:
A power converter, wherein power converter includes:
a first pair of semiconductor switches comprising a first semiconductor switch and a second semiconductor switch electrically connected to each other at a first electrical connection node; and
a second pair of semiconductor switches comprising a third semiconductor switch and a fourth semiconductor switch electrically connected to each other at a second electrical connection node, wherein the second semiconductor switch is electrically connected to the third semiconductor switch at a third electrical connection node;
wherein the at least one flying capacitor includes a first flying capacitor having a first terminal electrically connected to the first electrical connection node and a second terminal electrically connected to the second electrical connection node.
Regarding claims 10-18, the prior art fails to disclose or suggest the emboldened and italicized features below:
A power converter comprising:
a first pair of semiconductor switches comprising a first semiconductor switch and a second semiconductor switch electrically connected to each other at a first electrical connection node;
a second pair of semiconductor switches comprising a third semiconductor switch and a fourth semiconductor switch electrically connected to each other at a second electrical connection node, wherein the second semiconductor switch is electrically connected to the fourth semiconductor switch at a third electrical connection node; and
piezoelectric-resonator having a first terminal electrically connected to the third electrical connection node and a second terminal electrically coupled to an output terminal of the power converter.
Regarding claim 20, the prior art fails to disclose or suggest the emboldened and italicized features below:
A method,
wherein operating the plurality of semiconductor switches comprises controlling a switching operation of the semiconductor switches in a plurality of operation modes including at least seven connected operation modes in which the piezoelectric-resonator is electrically coupled across an input of the power converter, an output of the power converter, or a capacitor of the power converter and at least five open operation modes in which the piezoelectric-resonator is not coupled across the input of the power converter, the output of the power converter, or the capacitor of the power converter.
Conclusion
13. Any inquiry concerning this communication or earlier communications from the examiner should be directed to GARY NASH whose telephone number is (571) 270-3349. The examiner can normally be reached on Monday-Friday 8am-4pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner‘s supervisor, Thienvu Tran can be reached on (571) 270-1276. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
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/GARY A NASH/Primary Examiner, Art Unit 2838