Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Status of the Application
This Office Action is in response to Applicant’s Amendment filed on 10/14/2025.
Claims 1-7 are pending for this examination.
Claims 1 and 5 were amended.
Information Disclosure Statement
The information disclosure statements (IDSs) submitted on 9/03/2025; 10/23/2025; and 11/06/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over La Fratta et al. (US 2020/0065027), herein referred to as La Fratta ‘027, in view of Nazm Bojnordi et al. (US 2013/0282972), herein referred to as Nazm Bojnordi ‘972.
Referring to claim 1, La Fratta ‘027 teaches a memory system (see Fig. 1, memory subsystem 110) comprising:
a plurality of slots receiving a command input (see Fig. 1, command controller 113; see Paragraph 0027, wherein command controller 113 utilizes a command queue to receive, and schedule commands from the host system 120; also see Fig. 4, wherein a command queue is explicitly used to store commands from host) from an external host (see Fig. 1, host system 120);
a command processor (see Fig. 1, processor 117) configured to receive and process the command (see Paragraph 0026, wherein processor executes instructions stored in local memory 119 for performing operations described therein, and wherein command controller 113 stores parameters of received commands from the host 120 into local memory, see Paragraph 0027) from the plurality of slots according to a priority (see Paragraphs 0015-0019, wherein conventional memory subsystems implement strict first-ready, first-come, first-serve (FRFCFS) policy regarding command priority); and
a performance management circuit (see Fig. 1, memory system controller 115) including counter circuits respectively corresponding to the plurality of slots (see Paragraph 0032, wherein the processing device updates a bank touch count list, i.e. counter, that includes a list of banks being accessed by the commands in the command queue and the bank touch count for each of the banks in the list that identifies a number of commands accessing each of the banks respectively), activating a counter circuit corresponding to a slot to which the command is input among the plurality of slots in response to an input of the command (see Fig. 3; also see Paragraphs 0032-0035), and providing an interrupt signal requesting processing of the command to the command processor when a response corresponding to the command the command not provided to the host until a preset time is exceeded (see Paragraph 0027, wherein threshold parameters including a “maximum read command age”, which is a threshold specifying the amount of time a command can remain in the command queue before all other commands that access the same bank are to be blocked, and “hard maximum read command age”, which is the hard limit on the amount of time a command will sit in the command queue and be prevented from issuing by any other command on the same channel, are stored in local memory corresponding to the queued commands from host; Examiner points out that a threshold time limit before other commands are blocked from executing and thereby executing this specific command is the same thing as initiating an interrupt to pause all other command in order to execute the specific command, i.e. what is being described in La Fratta ‘027 is the same process as how an interrupt would work under the circumstances of a preset time being exceeded).
However, La Fratta ‘027 does not teach switching the counter circuit to an expiration state when a preset time is exceeded without a response corresponding to the command being provided to the host; and the interrupt being provided to the command processor in response to the expiration state of the counter circuit. (underlined sections of the above mapping of La Fratta ‘027 showing an interrupt being sent when “a response is not provided to the host until preset time is exceeded” whereas the amended claim language says the interrupt is sent in response to “the expiration state of the counter circuit” which is defined in the new limitation of the counter circuit being switched to an expiration state “when a preset time is exceeded without a response corresponding to the command being provided to the host”, which is the same)
Nazm Bojnordi ‘972 teaches a programmable memory controller system (see Abstract), wherein a processor is provided with 64 programmable counters which are used for capturing processor and queue states including the number of commands issued to the command queue, where every counter counts up and fires and interrupt when a pre-programmed threshold is reached, i.e. a time out or an expiration threshold, where one of two register operands can include the address of the interrupt service routine to handle the interrupt and the other register is used for specifying the counter value after which the counter interrupt must fire (see Paragraph 0085).
La Fratta ‘027 and Nazm Bojnordi ‘972 apply as analogous prior art as both pertain to the same field of endeavor of memory systems executing commands from a processor / host.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified La Fratta ‘027 system as set forth above to have the counters include a value after which an interrupt must be sent, i.e. an expiration value to which if the command has not received a response then an action of sending an interrupt is done, as taught by Nazm Bojnordi ‘972, as a person of ordinary skill in the art would be motivated to include the usage of timer-based interrupts for processing transactions to ensure a set time for checking / processing waiting transactions / commands and to ensure responsive operations to all commands which would ultimately save CPU cycles in comparison to normal methods of periodically polling to check if a command is still waiting response compared with a set time where the command would be processed through an interrupt regardless of what the CPU is doing.
As to claim 2, La Fratta ‘027 teaches the memory system of claim 1, wherein when the response corresponding to the command is provided to the host, the performance management circuit deactivates the counter circuit corresponding to the slot receiving the command (see Paragraph 0057, wherein a buffer is used to hold data from the memory components 112 before returning the data to the processing device in response to processing the command, where the count, which identifies the number of command accessing each bank (see Abstract), would be updated corresponding to the completion of executing a command, i.e. after the command is finished, it would no longer be queued so the count would be updated correspondingly).
As to claim 3, La Fratta ‘027 teaches the memory system of claim 1, wherein when the response corresponding to the command is not provided to the host until the preset time is exceeded (see Paragraph 0027, wherein threshold parameters including a “maximum read command age”, which is a threshold specifying the amount of time a command can remain in the command queue before all other commands that access the same bank are to be blocked, and “hard maximum read command age”, which is the hard limit on the amount of time a command will sit in the command queue and be prevented from issuing by any other command on the same channel, are stored in local memory corresponding to the queued commands from host; Examiner points out that a threshold time limit before other commands are blocked from executing and thereby executing this specific command is the same thing as initiating an interrupt to pause all other command in order to execute the specific command, i.e. what is being described in La Fratta ‘027 is the same process as how an interrupt would work under the circumstances of a preset time being exceeded), the performance management circuit stores information indicating a state of the command in a bitmap corresponding to the slot to which the command is input (see Paragraph 0027, wherein parameters corresponding to queued commands can be stored in local memory 119 and used to determine the status of the age of the command and what to do when it age hits its threshold).
As to claim 4, La Fratta ‘027 teaches the memory system of claim 3, wherein the performance management circuit outputs the interrupt signal based on information indicating the state of the command (see Paragraph 0027, wherein threshold parameters including a “maximum read command age”, which is a threshold specifying the amount of time a command can remain in the command queue before all other commands that access the same bank are to be blocked, and “hard maximum read command age”, which is the hard limit on the amount of time a command will sit in the command queue and be prevented from issuing by any other command on the same channel, are stored in local memory corresponding to the queued commands from host; Examiner points out that a threshold time limit before other commands are blocked from executing and thereby executing this specific command is the same thing as initiating an interrupt to pause all other command in order to execute the specific command, i.e. what is being described in La Fratta ‘027 is the same process as how an interrupt would work under the circumstances of a preset time being exceeded).
Referring to claim 5, La Fratta ‘027 teaches a storage device (see Fig. 1, system 100) comprising:
a memory device (see Fig. 1, memory subsystem 110);
a command manager configured to manage whether or not to perform a command received from an external command (see Fig. 1, command controller 113 and host 120 that is external to the memory subsystem 110; see Paragraph 0027, wherein command controller 113 utilizes a command queue to receive, and schedule commands from the host system 120; also see Fig. 4, wherein a command queue is explicitly used to store commands from host); and
a command processor (see Fig. 1, processor 117) configured to receive and process the command (see Paragraph 0026, wherein processor executes instructions stored in local memory 119 for performing operations described therein, and wherein command controller 113 stores parameters of received commands from the host 120 into local memory, see Paragraph 0027) according to a priority from the command manager (see Paragraphs 0015-0019, wherein conventional memory subsystems implement strict first-ready, first-come, first-serve (FRFCFS) policy regarding command priority),
wherein the command manager comprises:
a plurality of slots receiving a command input from an external host (see Fig. 1, command controller 113; see Paragraph 0027, wherein command controller 113 utilizes a command queue to receive, and schedule commands from the host system 120; also see Fig. 4, wherein a command queue is explicitly used to store commands from host); and
a performance management circuit (see Fig. 1, memory system controller 115) including counter circuits respectively corresponding to the plurality of slots (see Paragraph 0032, wherein the processing device updates a bank touch count list, i.e. counter, that includes a list of banks being accessed by the commands in the command queue and the bank touch count for each of the banks in the list that identifies a number of commands accessing each of the banks respectively), activating a counter circuit corresponding to a slot to which the command is input among the plurality of slots in response to an input of the command (see Fig. 3; also see Paragraphs 0032-0035), and providing an interrupt signal requesting processing of the command to the command processor when a response corresponding to the command is not provided to the host until a preset time is exceeded (see Paragraph 0027, wherein threshold parameters including a “maximum read command age”, which is a threshold specifying the amount of time a command can remain in the command queue before all other commands that access the same bank are to be blocked, and “hard maximum read command age”, which is the hard limit on the amount of time a command will sit in the command queue and be prevented from issuing by any other command on the same channel, are stored in local memory corresponding to the queued commands from host; Examiner points out that a threshold time limit before other commands are blocked from executing and thereby executing this specific command is the same thing as initiating an interrupt to pause all other command in order to execute the specific command, i.e. what is being described in La Fratta ‘027 is the same process as how an interrupt would work under the circumstances of a preset time being exceeded).
However, La Fratta ‘027 does not teach switching the counter circuit to an expiration state when a preset time is exceeded without a response corresponding to the command being provided to the host; and the interrupt being provided to the command processor in response to the expiration state of the counter circuit. (underlined sections of the above mapping of La Fratta ‘027 showing an interrupt being sent when “a response is not provided to the host until preset time is exceeded” whereas the amended claim language says the interrupt is sent in response to “the expiration state of the counter circuit” which is defined in the new limitation of the counter circuit being switched to an expiration state “when a preset time is exceeded without a response corresponding to the command being provided to the host”, which is the same)
Nazm Bojnordi ‘972 teaches a programmable memory controller system (see Abstract), wherein a processor is provided with 64 programmable counters which are used for capturing processor and queue states including the number of commands issued to the command queue, where every counter counts up and fires and interrupt when a pre-programmed threshold is reached, i.e. a time out or an expiration threshold, where one of two register operands can include the address of the interrupt service routine to handle the interrupt and the other register is used for specifying the counter value after which the counter interrupt must fire (see Paragraph 0085).
La Fratta ‘027 and Nazm Bojnordi ‘972 apply as analogous prior art as both pertain to the same field of endeavor of memory systems executing commands from a processor / host.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified La Fratta ‘027 system as set forth above to have the counters include a value after which an interrupt must be sent, i.e. an expiration value to which if the command has not received a response then an action of sending an interrupt is done, as taught by Nazm Bojnordi ‘972, as a person of ordinary skill in the art would be motivated to include the usage of timer-based interrupts for processing transactions to ensure a set time for checking / processing waiting transactions / commands and to ensure responsive operations to all commands which would ultimately save CPU cycles in comparison to normal methods of periodically polling to check if a command is still waiting response compared with a set time where the command would be processed through an interrupt regardless of what the CPU is doing.
As to claim 6, La Fratta ‘027 teaches the storage device of claim 5, wherein the command processor performs the command based on the interrupt signal (see Paragraph 0027, wherein threshold parameters including a “maximum read command age”, which is a threshold specifying the amount of time a command can remain in the command queue before all other commands that access the same bank are to be blocked, and “hard maximum read command age”, which is the hard limit on the amount of time a command will sit in the command queue and be prevented from issuing by any other command on the same channel, are stored in local memory corresponding to the queued commands from host; Examiner points out that a threshold time limit before other commands are blocked from executing and thereby executing this specific command is the same thing as initiating an interrupt to pause all other command in order to execute the specific command, i.e. what is being described in La Fratta ‘027 is the same process as how an interrupt would work under the circumstances of a preset time being exceeded).
As to claim 7, La Fratta ‘027 teaches the storage device of claim 5, wherein when the command processor provides the response corresponding to the command to the host, the performance management circuit deactivates the counter circuit corresponding to the slot receiving the command (see Paragraph 0057, wherein a buffer is used to hold data from the memory components 112 before returning the data to the processing device in response to processing the command, where the count, which identifies the number of command accessing each bank (see Abstract), would be updated corresponding to the completion of executing a command, i.e. after the command is finished, it would no longer be queued so the count would be updated correspondingly).
Response to Arguments
Applicant’s arguments, mailed 10/14/2025, have been fully considered but they are not deemed to be persuasive.
Applicant’s arguments that La Fratta ‘027 does not teach the new amended limitations of “switching the counter circuit to an expiration state when a preset time is exceeded without a response corresponding to the command being provided to the host” and sending the interrupt in response to the expiration state (see Pages 6-7) are moot in view of new grounds of rejection stated above that were necessitated by Applicant’s amendment. Examiner notes the arguments being made about the instant invention having the counter circuit using an activated “working” state and “expiration state”, however points out that the current claim language just requires a counter starting up, and switching to an expiration state when essentially a timeout event occurs due to no response corresponding to the command being provided to the host, i.e. the only state is the expiration state in the claim language. Basically Examiner is interpreting the current claim language as the claimed counter being a timer for sending an interrupt, which Examiner points out Nazm Bojnordi ‘972 teaches timer-based interrupts and set forth above.
In summary, La Fratta ‘027 in view of Nazm Bojnordi ‘972 teaches the claimed invention as set forth above.
Relevant Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Seong et al. (US 2021/0096773) teaches a method for operating a storage device with an external host and a memory controller having an operations controller and power controller.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL SUN whose telephone number is (571)270-1724. The examiner can normally be reached Monday-Friday 8am-4pm EST.
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/MICHAEL SUN/Primary Examiner, Art Unit 2183