DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 12/30/2025 have been fully considered but they are not persuasive.
The applicant contends, “The Office Action cites "claim 1 of U.S. Patent No. 18/094,398" as including limitations relating to receiving a write command, receiving address information of an external memory, and acquiring write data based on the address information. However, no issued claim of U.S. Patent No. 18/094,398 contains such subject matter.”
The Examiner would like to point out that the rejection is identical to the 102 rejection using PARK; Ie Ryung et al. (US 20230136664 A1). In addition, 18/094,398 is not a patent number, but instead is an application number. US 12379856 B2 is the published patent version of US 20230136664 A1 and the claims in the PG Pub are identical to the claims of the patent, the double patenting rejection mirrors 102 rejection using the PG Pub. Correction is made to the type of graphical error, below.
The Applicant contends that the prior art rejection is invalid because contrary to the Examiner’s position (the Examiner position is that support for limitations in claim 7 were introduced in the current Continuation in Part CIP and was not in the original parent application18/094,398), the parent case 18/094,398 provides support for the limitation “a memory controller configured to control the memory device based on a command received from an external host including a host memory, receive address information in the host memory from the external host, and access the host memory based on the address information in the host memory”. Support for this limitation is found in paragraph [0020] on page 8 of the current application. Paragraph [0012]-[0021] on pages 5-8 are newly added to the current application and did not exist in the parent application18/094,398.
The Applicant contends, that PARK; Ie Ryung et al. (US 20230136664 A1, hereafter referred to as PARK) is not a valid prior art based on date.
The Examiner would like to point out that 35 U.S.C. 102(a)(1) states A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. The Examiner would like to point out that the effective filing date of an individual claim in a CIP application is the date on which the subject matter of that claim was first disclosed in an application that meets the requirements of 35 U.S.C. 102(a). See MPEP 211.05. Since the subject matter of the current claims in the current application was first disclosed in the specification of the current application in paragraph [0020] on page 8, the effective filing date for the current application is 06/03/2024. Since the publication date of PARK; Ie Ryung et al. (US 20230136664 A1) is 5/4/2023, US 20230136664 A1 meets the requirements of35 U.S.C. 102(a)(1).
Election/Restrictions
Claims 1-6 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 09/16/2025.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 7 and 9-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by PARK; Ie Ryung et al. (US 20230136664 A1, hereafter referred to as PARK).
Rejection of claim 7:
claim 1 of the current application is directed to a storage device comprising
PARK is directed to a storage device comprising:
a memory device; and
a memory device; and
a memory controller configured to control the memory device based on a command received from an external host including a host memory, receive address information in the host memory from the external host, and access the host memory based on the address information in the host memory.
a memory controller configured to receive, from an external device having an external memory, a write command for storing a plurality of write data in the memory device and address information of an area in the external memory that corresponds to the write command, and acquire the plurality of write data from the external device based on the address information, Note: Figure 1 of PARK teaches that the external device is an external host and that the external memory is the host memory. In addition, paragraph [0008] on page 1 of PARK teaches that the memory controller is configured to receive address information from an area in the host memory that corresponds to the command.
Note: since the current application is a CIP of previous US application 18/094398 and the content of claim 1 was introduced in a CIP, but is not in US application 18/094398, the appropriate priority date for the current claims in the current application is 06/03/2024.
Rejection of claim 9:
Paragraph [0040] on page 3 PARK teaches the memory controller provides the external host with information on a position in the host memory.
Rejection of claim 10:
Paragraph [0008] on page 1 of PARK.
Rejection of claims 11-14:
Paragraph [0040] on page 3 PARK teaches the memory controller provides the external host with information on a position in the host memory.
Rejection of claim 15:
Paragraph [0052] on page 4 of PARK.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art. 2
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over PARK; Ie Ryung et al. (US 20230136664 A1, hereafter referred to as PARK) and Greenberger; Alan J. (US 20060041702 A1, hereafter referred to as Greenberger)
Rejection of claim 8:
Greenberger, in an analogous art, teaches the use of physical region descriptor tables (paragraph [0021] on page 2 of Greenberger).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine PARK with the teachings of Greenberger by including use of physical region descriptor tables. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, because one of ordinary skill in the art would have recognized that use of physical region descriptor tables would have provided use of bit level data transfers (paragraph [0021] on page 2 of Greenberger).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 7-15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-14 of U.S. Patent No. US 12379856 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because
claim 1 of the current application is directed to a storage device comprising
Claim 1 of U.S. Patent No. US 12379856 B2 is directed to a storage device comprising:
a memory device; and
a memory device; and
a memory controller configured to control the memory device based on a command received from an external host including a host memory, receive address information in the host memory from the external host, and access the host memory based on the address information in the host memory.
a memory controller configured to receive, from an external device having an external memory, a write command for storing a plurality of write data in the memory device and address information of an area in the external memory that corresponds to the write command, and acquire the plurality of write data from the external device based on the address information, Note: Figure 1 of U.S. Patent No. 18/094398 teaches that the external device is an external host and that the external memory is the host memory. In addition, column 2, lines 17-34 of U.S. Patent No. 18/094398 teaches that the memory controller is configured to receive address information from an area in the host memory that corresponds to the command.
Note: since the current application is a CIP of previous US application 18/094398 and the content of claim 1 was introduced in a CIP, but is not in US application 18/094398, the appropriate priority date for the current claims in the current application is 06/03/2024.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20160026388 A1 is directed toA data storage device, comprising: a nonvolatile memory; and a storage controller configured to fetch a first plurality of commands from at least one submission queue of a host memory, and fetch a plurality of pointers indicating a physical address of the host memory, wherein the plurality of pointers corresponds to the first plurality of commands, wherein the storage controller is configured to control a number of the plurality of pointers being fetched at substantially a same time based on determining whether a ratio of a second plurality of commands from among the first plurality of commands exceeds a reference ratio, wherein the second plurality of commands has a same property; and, is a good 103 reference.
US 20140164677 A1 is directed to A data storage device, comprising: a plurality of flash memory devices, each of the flash memory devices being arranged into a plurality of blocks having a plurality of pages for storing data; and a memory controller operationally coupled with the flash memory devices, the memory controller being configured to: receive a logical to physical address translation map from a host device, wherein a physical address includes a physical address for one of the flash memory devices; store the logical to physical address translation map in a memory module on the memory controller; receive read commands directly from an application running on the host device, wherein the read commands include logical memory addresses that refer to the logical locations on the flash memory devices; and translate the logical addresses to physical memory addresses using the logical to physical address translation map; and, is a good teaching reference.
US 20200242038 A1 is directed toA storage device comprising: a volatile memory comprising a plurality of sets of host memory configuration parameters, each set associated with a respective one of a plurality of hosts in communication with the storage device; means for, in response to receiving a command from a first host of the plurality of hosts, predicting a next host of the plurality of hosts from which a next command will arrive based on the received host command; and means for configuring the storage device with a set of host memory configuration parameters from the plurality of sets of host memory configuration parameters for the predicted next host prior to receiving the next command; and, is a good teaching reference.
US 20180024738 A1 is directed to A storage controller, configured to control a storage device having a rewritable non-volatile memory module, the storage controller comprising: a connection interface circuit, configured to couple to a host system, wherein the host system has a host memory, wherein the host memory has a plurality of memory pages; a memory interface control circuit, configured to couple to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module is assigned with a plurality of logical blocks; a processor, coupled to the connection interface circuit and the memory interface control circuit; and a data transfer management circuit, coupled to the processor, the connection interface circuit and the memory interface control circuit, wherein the processor is configured to receive a write command from the host system, wherein the write command comprises a starting logical block address, a number of logical blocks, a first physical region page pointer, and a second physical region page pointer, wherein the write command is configured to write target data into at least one target logical block of the rewritable non-volatile memory module, wherein a foremost logical block sorted in the at least one target logical block is a starting logical block, wherein the starting logical block address is configured to indicate an address of the starting logical block, the number of logical blocks is configured to indicate a number of the logical blocks storing the target data in the at least one target logical block, the first physical region page pointer is configured to indicate a first memory page address of the host memory, and the second physical region page pointer is configured to indicate a second memory page address of the host memory, wherein the target data corresponding to the write command is stored in at least one target memory page among the memory pages of the host memory, wherein the processor is configured to instruct the data transfer management circuit to obtain an address of each of the target memory pages respectively corresponding to the at least one target logical block according to the starting logical block address, the number of logical blocks, the first physical region page pointer, and the second physical region page pointer, wherein each of the target memory pages respectively corresponding to the target logical blocks is one of the at least one target memory page, wherein the memory interface control circuit is configured to select a first target logical block from the at least one target logical block, wherein the data transfer management circuit is configured to read first target data according to the obtained address of a first target memory page corresponding to the first target logical block, and the memory interface control circuit is further configured to write the read first target data into the first target logical block; and, is a good 103 reference.
US 20170357572 A1 is directed to A memory controller, comprising: a controller memory configured to store data corresponding to an area allocated to a memory in the memory controller configured to control the memory; an access control unit configured to allocate a partial area of the controller memory to a host memory in a host computer and use the area as a memory extension area; and an extension area managing unit configured to perform management in which a size of the memory extension area in the host memory is changeable; and, is a good teaching reference.
US 20180052634 A1 is directed to A storage controller, configured to control a storage device having a rewritable non-volatile memory module, the storage controller comprising: a connection interface circuit, configured to couple to a host system, wherein the host system has a host memory, wherein the host memory has a plurality of memory pages; a memory interface control circuit, configured to couple to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module is assigned with a plurality of logical blocks; a processor, coupled to the connection interface circuit and the memory interface control circuit; a data transfer management circuit, coupled to the processor, the connection interface circuit and the memory interface control circuit; a list management circuit, coupled the data transfer management circuit, the processor, the connection interface circuit and the memory interface control circuit, wherein the processor is configured to receive a transmission command from a host system, wherein the transmission command comprises a starting logical block address (SLBA), a number of logical blocks (NLB), a first physical region page pointer (PRP1), and a second physical region page pointer (PRP2), wherein the transmission command is configured to transmit target data between at least one target logical block of the rewritable non-volatile memory module and at least one target memory page of the host memory, wherein the starting logical block address is configured to indicate an address of the foremost target logical block in the at least one target logical block, the number of logical blocks is configured to indicate a number of the logical blocks storing the target data in the at least one target logical block, the first physical region page pointer is configured to indicate a first memory page address of the host memory, and the second physical region page pointer is configured to indicate a second memory page address of the host memory, wherein if the second memory page address is a first list starting address of a first physical region page pointer list of at least one physical region page pointer list corresponding to the transmission command, the list management circuit is configured to read a part of the at least one physical region page pointer list from the host memory according to the transmission command, and buffer the read part of the at least one physical region page pointer list, wherein the data transfer management circuit is configured to transmit corresponding data according to the buffered part of the at least one physical region page pointer list, wherein the transmitted data is a part of the target data; and, is a good 103 reference.
US 20140164676 A1 is directed to A data storage device, comprising: a plurality of flash memory devices, each of the flash memory devices being arranged into a plurality of blocks having a plurality of pages for storing data; and a memory controller operationally coupled with the flash memory devices, the memory controller being configured to: receive a virtual to physical memory address translation map from a host device, wherein a physical memory address includes a physical address for memory on the host device; store the virtual to physical memory address translation map in a memory module on the memory controller; receive commands directly from an application running on the host device, wherein the commands include virtual memory addresses that refer to the memory on the host device; and translate the virtual memory addresses to physical memory addresses using the virtual to physical memory address translation map; and, is a good teaching reference.
US 20190235790 A1 is directed to An electronic system comprising: a host configured to queue an external command to wait or to be output, based on a status of dies included in a storage device; a central processing unit configured to generate a command for controlling the storage device in response to a request received from the host or the external command; and a controller memory buffer configured to store status information indicating whether the dies are in a status in which access is possible or a status in which access is impossible, wherein the central processing unit receives status information of the dies from the storage device, and stores status information matched to each of the dies in the controller memory buffer; and, is a good teaching reference.
US 20230109300 A1 is directed to A system comprising: a storage device including a nonvolatile memory and a storage controller; and a host device including a host memory, a core and a host controller, and configured to communicate with the storage device through a Universal Flash Storage (UFS) protocol, wherein the host controller is configured to generate a plurality of commands including a first command, to transfer the plurality of commands to circular queues in the host memory, to determine an order of transferring to the storage device the plurality of commands stored in the circular queues, and the host controller is configured to store a head pointer and a tail pointer for each queue of the circular queues; and, is a good 103 reference.
US 20170131917 A1 is directed to A storage device connected to a host through an interface sharing a memory buffer of the host, the storage device comprising: a plurality of nonvolatile memory devices; an internal buffer for buffering data being exchanged with the host; and a storage controller that anticipates data expected to be subsequently requested by the host with reference to an access command from the host and reads out the anticipated data from the nonvolatile memory devices or the internal buffer to load the read data in a source area of the memory buffer; and, is a good teaching reference.
US 20160328567 A1 is directed toA system for descrambling and scrambling data transmitted via a memory channel of a memory device coupled to a host system, comprising: a storage device driver installed on the host system that executes a training mode for the memory device to discover XOR vectors used by the host system to scramble data by: inputting all zero training data to a scrambling algorithm for all memory locations of the memory device to generate scrambled training data that is transmitted over the memory channel to the memory device, such that the scrambled training data are equal to the XOR vectors corresponding to those memory locations; and a storage controller on the memory device configured to: receive the scrambled training data over the memory channel and store the scrambled training data as the XOR vectors for each of the corresponding memory locations; and after the training mode and during a functional mode of the memory device, receive scrambled data over the memory channel for a specified memory location, and use the XOR vector stored for the specified memory location to descramble the scrambled data prior to writing to the specified memory location; and, is a good teaching reference.
US 20220100681 A1 is directed to A method comprising: receiving, by a storage controller coupled to a storage device, a read command referencing a data block; and performing in parallel: (a) generating a data structure representing a linked list of buffer locations within a host memory corresponding to the data block; and (b) reading the data block from the storage device; and, is a good 103 reference.
US 20200218605 A1 is directed to A storage device comprising: a communication means configured to connect to a host system; non-volatile memory means; volatile memory means; and processing means associated with the non-volatile memory, the processing means configured to: receive data from the host system for storing in the non-volatile memory means; buffer the data in the volatile memory means; obtain parity data corresponding to the buffered data from an external volatile memory within the host system; compute XOR parity data for the buffered data based on the parity data and the buffered data; store the computed XOR parity data on the external volatile memory; and write the data from the host to the external non-volatile memory; and, is a good teaching reference.
US 10970235 B2 is directed to A computing system comprising: a host device configured to send a plurality of Input/Output (I/O) requests through a peripheral component interconnect express (PCIe) root complex and comprising a memory sub-system configured to store, in a submission queue, command entries corresponding to the plurality of I/O requests, respectively; and a storage device connected to the host device, the storage device comprising at least one nonvolatile memory device and a memory controller configured to control the at least one nonvolatile memory device, wherein the memory sub-system comprises: a data array used by the host device, and a host memory buffer used by the storage device, wherein the host memory buffer comprises: a metadata area that stores metadata for managing the storage device, and a data cache area that temporarily stores data corresponding to the plurality of I/O requests, wherein the storage device is further configured to: fetch a command entry corresponding to an I/O request, among the plurality of I/O requests, from the submission queue; and send, to the host device, a data movement request between the data array and the data cache area based on the I/O request, wherein the host device is further configured to transfer the data between the data array and the data cache area based on the data movement request of the storage device, and wherein the storage device is further configured to update a completion status of the I/O request, as the I/O request being completed, after the transferring the data; and, is a good 103 reference.
US 10387078 B1 is directed to A data storage controller for use with a data storage device, comprising: a processing system configured to determine a current queue depth for a queue used by a host device to issue commands to the data storage controller, where the host device is configured to control the issuance of the commands based on queue depth, determine a modified queue depth for reporting to the host device that is different from the current queue depth, and control the issuance of additional commands from the host device to the data storage controller by reporting the modified queue depth to the host device rather than the current queue depth; and, is a good teaching reference.
US 8255618 B1 is directed to A system comprising: a host device comprising a plurality of host memory operation queues; and a data storage device operationally coupled with the host device, the data storage device comprising: a plurality of flash memory devices; a memory controller operationally coupled with the plurality of flash memory devices, the memory controller comprising: a queue arbiter configured to obtain, from the host memory operation queues, memory operation commands for execution by the data storage device; a command dispatcher operationally coupled with the queue arbiter, the command dispatcher being configured to: receive the memory operation commands from the queue arbiter in a same order as obtained by the queue arbiter from the host device; separately and respectively queue the memory operation commands for each of the plurality of flash memory devices; and dispatch the memory operation commands for execution by the plurality of flash memory devices; a plurality of memory device command queues operationally coupled with the command dispatcher, each memory device command queue being associated with a respective one of the plurality of flash memory devices and configured to: receive the dispatched memory operation commands corresponding with its respective memory device from the command dispatcher in a same order as received by the command dispatcher; and provide the received memory operation commands to its respective flash memory device in a first-in-first-out order; and, is a good 103 reference.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH D TORRES whose telephone number is (571)272-3829. The examiner can normally be reached Monday-Friday 10-7 PT.
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/JOSEPH D TORRES/Primary Examiner, Art Unit 2112