DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This non-final office action is responsive to Applicants' application filed on 06/03/24. Claims 1-20 are presented for examination and are pending for the reasons indicated herein below.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4-6, 11-12, 15, 17, 20 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mercer et al. (US 20230198385 A1)
Regarding claim 1. Mercer teaches a power supply device [fig 1a] comprising: a three-level converting circuit [¶4, S1-S4 path and S5-S8 path make a converting circuit] including a flying capacitor [C1A/C2A] configured for three-level operation, the three-level converting circuit configured to generate an intermediate voltage [voltage applied to upper terminal of L1] based on an input voltage, a plurality of first control signals [signals applied to switches s1, s4, s10, s5, s8, s11] and the flying capacitor;
a dual path hybrid converting circuit including a first path [C1B w/ S2 path], a second path [C2B w/ S6 path], an inductor [L2] in the first path and a hybrid capacitor [hybrid power conditions can be met according to ¶38 and using C2B or C1B] in the second path, the dual path hybrid converting circuit configured to generate an output voltage [Vout] based on the intermediate voltage, a second control signal [signals applied to S2-S3 or S6-S7], the inductor and the hybrid capacitor, both the first path and the second path being connected to an output node providing the output voltage, the first path and the second path being different from each other [paths connected through s3 and s7];
and an auxiliary switch [s9] circuit between [i.e. being in the middle] the three-level converting circuit and the dual path hybrid converting circuit, the auxiliary switch circuit configured to control current flow through the hybrid capacitor based on a third control signal [signal applied to s9], wherein the power supply device is configured to selectively operate based on a four-phase scheme and a six-phase scheme depending on an operation mode [each figures 2 or 3 or 4 or 6 can be 1 phase scheme].
Regarding claim 4. Mercer teaches the power supply device [connected between has been interpreted as connected between intervening elements] of claim 1, wherein the three-level converting circuit further comprises: a first transistor [s1] connected between the input voltage and a first node [bottom node];
a second transistor [s2] connected between the first node and a second node [i.e. LX2];
a third transistor [s2] connected between the second node and a third node;
and a fourth transistor [s8] connected between the third node and a ground voltage, and wherein the flying capacitor is connected between the first node and the third node.
Regarding claim 5. Mercer teaches the power supply device of claim 4, wherein the dual path hybrid converting circuit further comprises: a fifth transistor [s3] connected between a fourth node and the output node, wherein the inductor is connected between the second node [i.e. LX2 node] and the output node, and wherein the hybrid capacitor is connected between the second node and the fourth node [C1B].
Regarding claim 6. Mercer teaches the power supply device of claim 5, wherein the auxiliary switch circuit comprises: a sixth transistor [s9] connected between the third node and the fourth node, and a body bias voltage [voltage at source terminal] applied to the sixth transistor being changeable.
Regarding claim 11. Mercer teaches the power supply device of claim 1, further comprising: a control signal generating circuit [¶36] configured to generate the plurality of first control signals, the second control signal and the third control signal.
Regarding claim 12. Mercer teaches the power supply device of claim 11, wherein the control signal generating circuit comprises: a first comparator configured to generate a first signal by comparing the output voltage with a reference voltage [¶76];
a duty generator [i.e. pwm generator] configured to generate a plurality of phase signals based on the first signal;
and a switch logic [logic generator in 120 disclose in ¶118] and gate driver configured to generate the plurality of first control signals, the second control signal and the third control signal based on the plurality of phase signals.
Regarding claim 15. Mercer teaches the power supply device of claim 1, wherein the operation mode is determined based on a conversion ratio obtained by dividing the output voltage by the input voltage [i.e. feedback determines required regulation, ¶35, ¶67].
Regarding claim 17. Mercer teaches the power supply device of claim 1, wherein a voltage level of the output voltage is lower than a voltage level of the input voltage [¶138].
Regarding claim 20. Mercer teaches a power supply device [fig 1a] comprising: a first transistor connected between an input voltage [vin] and a first node;
a second transistor [s1] connected between the first node and a second node [lower terminal], the second node providing an intermediate voltage;
a third transistor [s2] connected between the second node and a third node [left terminal];
a fourth transistor [s8] connected between the third node [upper terminal of s8] and a ground voltage;
a flying capacitor [C1A/C2A] connected between the first node and the third node;
an inductor [L2] connected between the second node [LX2 node] and an output node [vout], the output node providing an output voltage;
a hybrid capacitor [C2B, hybrid power conditions can be met according to ¶38 and using C2B or C1B] connected between the second node [LX2 node] and a fourth node [lower node];
a fifth transistor [s3] connected between the fourth node and the output node;
a sixth transistor [s9] connected between the third node and the fourth node, and a body bias voltage [voltage at source terminal] applied to the sixth transistor being changeable;
and an output capacitor [cout] connected between the output node and the ground voltage, wherein the first, second, third and fourth transistors and the flying capacitor are configured to perform three-level operation [¶4], wherein the inductor is included in a first path [101], the first path being connected to the output node, wherein the hybrid capacitor is included in a second path [i.e. patch C1B w/ S2], the second path being connected [i.e. connected through S3] to the output node, wherein the power supply device is configured to generate the output voltage using a dual path including the first and second paths, and wherein the power supply device is configured to selectively operate based on a four-phase scheme and a six-phase scheme based on a conversion ratio obtained by dividing the output voltage by the input voltage [each figures 2 or 3 or 4 or 6 can be 1 phase scheme].
Allowable Subject Matter
Claims 2-3,7-10,13-14 and 16 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if the claim objections stated above were overcome.
Claims 18-19 are allowed.
Regarding claim 18. Parto (20170331371) teaches a memory module [fig 7A] comprising: a circuit board [701]; a plurality of memory [see mems on 7A] devices on the circuit board; and a power supply device [707] on the circuit board, the power supply device configured to provide a power supply voltage to the plurality of memory devices, wherein the power supply device comprises a three-level converting circuit [¶70] including a flying capacitor for three-level operation, the three-level converting circuit configured to generate an intermediate voltage based on an input voltage [input to 707].
The following is an examiner' s statement of reasons for allowance: The prior art does not disclose or suggest, in combination with the limitations of the base claim and any intervening claims, primarily, “…a plurality of first control signals and the flying capacitor, a dual path hybrid converting circuit including a first path, a second path, an inductor in the first path and a hybrid capacitor in the second path, the dual path hybrid converting circuit configured to generate an output voltage based on the intermediate voltage, a second control signal, the inductor and the hybrid capacitor, both the first path and the second path being connected to an output node providing the output voltage, the first path and the second path being different from each other, the output voltage corresponding to the power supply voltage, and an auxiliary switch circuit between the three-level converting circuit and the dual path hybrid converting circuit, the auxiliary switch circuit configured to control current flow through the hybrid capacitor based on a third control signal, wherein the power supply device is configured to selectively operate based on a four-phase scheme and a six-phase scheme depending on an operation mode.”
Examiner Note
The examiner cites particular columns and lines numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Bryan Perez whose telephone number is (571)272-8837. The examiner can normally be reached on Mon.-Fri. (7:30 – 5:00).
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Crystal Hammond, can be reached on (571) 270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRYAN R PEREZ/Examiner, Art Unit 2838
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