Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is in response to the amendments filed on 05/20/2026, in which claims 1-20 are presented for the examination.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4, 8-12, 16, 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 2022/0113889, referred herein after Park) in view of Schaefer (US 2023/0395173).
As per claim 1, 16, Park discloses a memory device, comprising: one or more hardware components or a controller configured to:
read one or more bits, before performing a memory built-in self-test, that are stored in a mode register of the memory device (Fig. 1, 2, [0076], The control circuit 124 may include a mode register MRS providing a plurality of operational options of the memory device 120 and a test mode register TMRS providing test operational options. An MRS/TMRS 212 may program various functions, characteristics, and modes of the memory device 120. Test mode options (e.g., a DDR test mode or a PBT test mode) to be performed by the MBIST circuit 126, may be selectively set by the MRS/TMRS 212 )
perform the memory built-in self-test using the one or more memory resources (Fig. 2, 3, [0094], Referring to FIGS. 2 and 3, an MBIST option may be set in operation S310 and, according to set MBIST option, a PBT test may be performed by the MBIST circuit 126 in operation S320 or a DDR test may be performed by the MBIST circuit 126 in operation S330.);
Park does not specifically disclose the one or more bits indicate one or more memory resources, including indicating a number of addressable memory resources, of the memory device for performing the memory built-in self-test; and
wherein the one or more bits are written to the mode register by a host device to control the number of addressable memory resources;
However, Schaefer discloses wherein the one or more bits indicate one or more memory resources, including indicating a number of addressable memory resources, of the memory device for performing the memory built-in self-test; and (abstract, (abstract, Fig. 4, 410, 420, 430, , [0050], [0052], second sets of bits identify memory sections for which MBIST is to be performed, the memory sections being a subset of a plurality of memory sections. Thus, the bits indicate one or more addressable memory resources);
wherein the one or more bits are written to the mode register by a host device to control the number of addressable memory resources ([0052], host device write to section identifier mode register 430 to control MBIST operations, [0054], the values in the register identify a subset of memory sections for MBIST);
Therefore it would have been obvious to the one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate teaching of Schaefer’s memory section selection for MBIST into Park’s method of testing a memory device, a MBIST circuit because one of the ordinary skill in the art would have been motivated to improve reliability of the memory device and improve operation of the automotive system.
As per claim 2, Park discloses the memory device of claim 1, wherein the one or more memory resources are associated with performing standard memory operations of the memory device (Fig. 2, [0071], [0072], [0075], memory device 120 performs standard memory operations as claimed).
As per claim 3, 11, Park discloses the system of claim 2, wherein the one or more memory resources are not used for performing standard memory operations of the memory device based on the one or more bits ([0104], [0105], memory resources are disabled by programming using patterns and in test mode, memory resources are not used to perform standard memory operations as claimed).
As per claim 4, Park discloses the memory device of claim 1, wherein the one or more memory resources correspond to one or more rows of the memory device ([0059], memory cell has corresponding rows and columns).
As per claim 8, Park discloses a system, comprising: a host device comprising one or more hardware components that are configured to: transmit, to a memory device, and the memory device, comprising one or more hardware components or a controller to:
read the one or more bits from the mode register of the memory device before performing the memory built-in self-test; and (Fig. 1, 2, [0076], The control circuit 124 may include a mode register MRS providing a plurality of operational options of the memory device 120 and a test mode register TMRS providing test operational options. An MRS/TMRS 212 may program various functions, characteristics, and modes of the memory device 120. Test mode options (e.g., a DDR test mode or a PBT test mode) to be performed by the MBIST circuit 126, may be selectively set by the MRS/TMRS 212 );
perform the memory built-in self-test using the one or more memory resources of the memory device (Fig. 2, 3, [0094], Referring to FIGS. 2 and 3, an MBIST option may be set in operation S310 and, according to set MBIST option, a PBT test may be performed by the MBIST circuit 126 in operation S320 or a DDR test may be performed by the MBIST circuit 126 in operation S330.);
Park does not specifically disclose a command to write one or more bits to a mode register of the memory device to indicate one or more memory resources, including indicating a number of addressable memory resources, of the memory device for performing a memory built-in self-test;
wherein the one or more bits are written to the mode register by a host device to control the number of addressable memory resources;
However, Schaefer discloses a command to write one or more bits to a mode register of the memory device to indicate one or more memory resources, including indicating a number of addressable memory resources, of the memory device for performing a memory built-in self-test; (abstract, Fig. 4, 410, 420, 430, , [0050], [0052], second sets of bits identify memory sections for which MBIST is to be performed, the memory sections being a subset of a plurality of memory sections. Thus, the bits indicate one or more addressable memory resources);
wherein the one or more bits are written to the mode register by a host device to control the number of addressable memory resources ([0052], host device write to section identifier mode register 430 to control MBIST operations, [0054], the values in the register identify a subset of memory sections for MBIST);
Therefore it would have been obvious to the one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate teaching of Schaefer’s memory section selection for MBIST into Park’s method of testing a memory device, a MBIST circuit because one of the ordinary skill in the art would have been motivated to improve reliability of the memory device and improve operation of the automotive system.
As per claim 9, Park discloses the system of claim 8, wherein the one or more memory resources are addressable memory resources ([0059], memory controller access memory device and physical address is provided to access the memory).
As per claim 10, Park discloses the system of claim 9, wherein the one or more memory resources are no longer addressable based on the one or more bits ([0104], [0105], memory resources are disabled by programming using patterns).
As per claim 12, Park discloses the system of claim 8, wherein the one or more bits are included in a plurality of bits indicated by the command and read from the mode register of the memory device (Fig. 3, [0094], MBIST option set by programming MRS).
As per claim 18, Park discloses the method of claim 16, wherein the mode register of the memory device includes one or more other bits indicating whether the memory built-in self-test is enabled ([0014], [0076], [0077], setting patterns in enable state indicates MBIST is enabled).
As per claim 19, Park discloses the method of claim 18, wherein the one or more other bits further indicate whether an error-correcting code is enabled for the memory built-in self-test ([0141], MRS setting error correction code (ECC) function).
Claims 5-7, 13-14, 17 are rejected under 35 U.S.C. 103 as being unpatentable over Park and Schaefer in view of Nale (US 2020/0176072).
As per claim 5, neither Park nor Schaefer specifically disclose the memory device of claim 1, wherein the one or more bits are indicative of a quantity of memory resources of the memory device that are associated with performing the memory built-in self-test;
However, Nale discloses the one or more bits are indicative of a quantity of memory resources of the memory device that are associated with performing the memory built-in self-test ([0031]-[0034]).
Therefore it would have been obvious to the one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate teaching of Nale’s DRAM BIST power fail mitigation system into Park’s method of testing a memory device and Schaefer’s memory section selection for MBIST because one of the ordinary skill in the art would have been motivated to improve reliability and reducing test time.
As per claim 6, neither Park nor Schaefer specifically disclose the memory device of claim 1, wherein the one or more hardware components or a controller are configured to perform the memory built-in self-test using one or more other memory resources of the memory device that are configured only for performing the memory built-in self-test;
However, Nale discloses the one or more hardware components or a controller are configured to perform the memory built-in self-test using one or more other memory resources of the memory device that are configured only for performing the memory built-in self-test ([0031], [0033], [0036], 0037]).
Therefore it would have been obvious to the one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate teaching of Nale’s DRAM BIST power fail mitigation system into Park’s method of testing a memory device and Schaefer’s memory section selection for MBIST because one of the ordinary skill in the art would have been motivated to improve reliability and reducing test time.
As per claim 7, neither Park nor Schaefer specifically disclose the memory device of claim 1, wherein the one or more hardware components or a controller are configured to perform the memory built-in self-test for one or more memory sections of the memory device that do not include the one or more memory resources;
However, Nale discloses the one or more hardware components or a controller are configured to perform the memory built-in self-test for one or more memory sections of the memory device that do not include the one or more memory resources ([0032], [0034], [0036]).
Therefore it would have been obvious to the one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate teaching of Nale’s DRAM BIST power fail mitigation system into Park’s method of testing a memory device and Schaefer’s memory section selection for MBIST because one of the ordinary skill in the art would have been motivated to improve reliability and reducing test time.
As per claim 13, neither Park nor Schaefer specifically disclose the system of claim 12, wherein the plurality of bits includes at least a first bit that corresponds to a first memory section of the memory device and a second bit that corresponds to a second memory section of the memory device;
However, Nale discloses the plurality of bits includes at least a first bit that corresponds to a first memory section of the memory device and a second bit that corresponds to a second memory section of the memory device ([0025]-[0026]);
Therefore it would have been obvious to the one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate teaching of Nale’s DRAM BIST power fail mitigation system into Park’s method of testing a memory device and Schaefer’s memory section selection for MBIST because one of the ordinary skill in the art would have been motivated to improve reliability and reducing test time.
As per claim 14, Park discloses the system of claim 13, wherein the second memory section includes the first memory section and one or more other memory sections ([0025]-[0026]).
As per claim 17, neither Park nor Schaefer specifically disclose the method of claim 16, wherein the one or more rows include an initial set of one or more rows of the memory device or a last set of one or more rows of the memory device;
However, Nale discloses the one or more rows include an initial set of one or more rows of the memory device or a last set of one or more rows of the memory device ([0002], [0025]);
Therefore it would have been obvious to the one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate teaching of Nale’s DRAM BIST power fail mitigation system into Park’s method of testing a memory device and Schaefer’s memory section selection for MBIST because one of the ordinary skill in the art would have been motivated to improve reliability and reducing test time.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Park and Schaefer in view of Gallgher et al. (US 10,706,950, referred herein after Gallagher).
As per claim 15, neither Park nor Schaefer specifically disclose the system of claim 8, wherein one or more hardware components or the controller of the memory device are configured to perform the memory built-in self-test for fewer than all memory sections associated with the memory device;
However, Gallagher discloses one or more hardware components or the controller of the memory device are configured to perform the memory built-in self-test for fewer than all memory sections associated with the memory device (Col. 4, lines 9-31, Col. 6, lines 11-28);
Therefore it would have been obvious to the one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate teaching of Gallagher’s testing for memory error correction code logic into Park’s method of testing a memory device and Schaefer’s memory section selection for MBIST because one of the ordinary skill in the art would have been motivated to provide improved testing of memory error correction code (“ECC”) logic with memory built-in self-test (“MBIST”).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Park and Schaefer in view of Fischer et al. (US 2010/0157703, referred herein after Fishcher).
As per claim 20, neither Park nor Schaefer specifically disclose the method of claim 16, wherein the mode register of the memory device includes one or more other bits indicating whether a repair mode of the memory device is enabled;
However, Fischer discloses the mode register of the memory device includes one or more other bits indicating whether a repair mode of the memory device is enabled ([0038]-[0040]);
Therefore it would have been obvious to the one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate teaching of Fischer’s embedded memory repair method into Park’s method of testing a memory device and Schaefer’s memory section selection for MBIST because one of the ordinary skill in the art would have been motivated to provide improved testing of memory error correction code (“ECC”) logic with memory built-in self-test (“MBIST”).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAMINI B PATEL whose telephone number is (571)270-3902. The examiner can normally be reached on M-F 8-4:30.
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/KAMINI B PATEL/Primary Examiner, Art Unit 2114
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