Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is in response to the RCE filed on 10/10/2025, in which claims 1-20 are presented for the examination.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10/10/2025 has been entered.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 8, 16 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 12, 20 of U.S. Patent No. 12,530,139 respectively. Although the claims at issue are not identical, they are not patentably distinct from each other.
Instant application
Referenced patent (12,530139)
1. (Previously Presented) A memory device, comprising: one or more hardware components or a controller configured to:
read one or more bits, before performing a memory built-in self-test, that are stored in a mode register of the memory device,
wherein the one or more bits indicate one or more memory resources of the memory device for performing the memory built-in self-test; and
perform the memory built-in self-test using the one or more memory resources.
8. (Previously Presented) A system, comprising: a host device comprising one or more hardware components that are configured to:
transmit, to a memory device, a command to write one or more bits to a mode register of the memory device to indicate one or more memory resources of the memory device for performing a memory built-in self-test; and
the memory device, comprising one or more hardware components or a controller configured to:
read the one or more bits from the mode register of the memory device before performing the memory built-in self-test; and
perform the memory built-in self-test using the one or more memory resources of the memory device.
16. (Original) A method comprising:
reading one or more bits, before performing a memory built-in self-test, that are stored in a mode register of a memory device, wherein the one or more bits indicate one or more rows of the memory device for performing the memory built-in self-test; and performing the memory built-in self-test using the one or more rows of the memory device.
1. A memory device, comprising: one or more components configured to:
read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device;
based on reading the one or more bits that are stored in the mode register of the memory device, perform the memory built-in self-test;
perform the memory built-in self-test for one or more memory sections of the memory device based on reading the one or more bits that are stored in the mode register of the memory device, wherein performing the memory built-in self-test comprises testing for single-bit errors associated with the one or more memory sections of the memory device; identify a plurality of single-bit errors associated with the one or more memory sections of the memory device based on performing the memory built-in self-test, wherein the plurality of single-bit errors includes a first quantity of time-zero single-bit errors that exist in the one or more memory sections prior to the memory device being accessed by a user and a second quantity of single-bit errors that are identified after the memory device has been accessed by the user; repair one or more time-zero single-bit errors of the first quantity of single-bit errors based on identifying the plurality of single-bit errors; write a value that indicates the second quantity of single-bit errors to a location in the memory device after repairing the one or more time-zero single-bit errors; and transmit, to a host device, an indication of the location to which the value was written.
12. A system, comprising: a host device configured to:
transmit a mode register write command to write one or more bits, associated with a memory built-in self-test, to a mode register of a memory device; and
the memory device configured to: read the one or more bits that are stored in the mode register of the memory device;
perform the memory built-in self-test for one or more memory sections of the memory device based on reading the one or more bits that are stored in the mode register of the memory device, wherein performing the memory built-in self-test comprises testing for single-bit errors associated with the one or more memory sections of the memory device; identify a plurality of single-bit errors associated with the one or more memory sections of the memory device based on performing the memory built-in self-test, wherein the plurality of single-bit errors includes a first quantity of time-zero single-bit errors that exist in the one or more memory sections prior to the memory device being accessed by a user and a second quantity of single-bit errors that are identified after the memory device has been accessed by the user; repair one or more time-zero single-bit errors of the first quantity of single-bit errors based on identifying the plurality of single-bit errors; write a value that indicates the second quantity of single-bit errors to a location in the memory device after repairing the one or more time-zero single-bit errors; and transmit, to the host device, an indication of the location to which the value was written.
20. A method comprising:
reading one or more bits, associated with a memory built-in self-test, that are stored in a mode register of a memory device; performing the memory built-in self-test for one or more memory sections of the memory device based on reading the one or more bits that are stored in the mode register of the memory device, wherein performing the memory built-in self-test comprises testing for single-bit errors associated with the one or more memory sections of the memory device; completing the memory built-in self-test; repairing all time-zero single-bit errors that are identified by the memory built-in self-test, wherein the time-zero single-bit errors include single-bit errors that exist in the one or more memory sections prior to the memory device being accessed by a user; writing, to a location in the memory device, a value that indicates a number of single-bit errors associated with the one or more memory sections of the memory device based on completing the memory built-in self-test and after repairing the time-zero single-bit errors that are identified by the memory built-in self-test, wherein the number of single-bit errors includes single-bit errors that are identified after the memory device has been accessed by the user; and transmitting an indication of the location to which the value was written.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 8-12, 16, 18-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al. (US 2022/0113889, referred herein after Park).
As per claim 1, 16, Park discloses a memory device, comprising: one or more hardware components or a controller configured to:
read one or more bits, before performing a memory built-in self-test, that are stored in a mode register of the memory device (Fig. 1, 2, [0076], The control circuit 124 may include a mode register MRS providing a plurality of operational options of the memory device 120 and a test mode register TMRS providing test operational options. An MRS/TMRS 212 may program various functions, characteristics, and modes of the memory device 120. Test mode options (e.g., a DDR test mode or a PBT test mode) to be performed by the MBIST circuit 126, may be selectively set by the MRS/TMRS 212 ) wherein the one or more bits indicate one or more memory resources of the memory device for performing the memory built-in self-test; and (MRS/TMRS 212 selectively set to perform MBIST);
perform the memory built-in self-test using the one or more memory resources (Fig. 2, 3, [0094], Referring to FIGS. 2 and 3, an MBIST option may be set in operation S310 and, according to set MBIST option, a PBT test may be performed by the MBIST circuit 126 in operation S320 or a DDR test may be performed by the MBIST circuit 126 in operation S330.).
As per claim 2, Park discloses the memory device of claim 1, wherein the one or more memory resources are associated with performing standard memory operations of the memory device (Fig. 2, [0071], [0072], [0075], memory device 120 performs standard memory operations as claimed).
As per claim 3, 11, Park discloses the system of claim 2, wherein the one or more memory resources are not used for performing standard memory operations of the memory device based on the one or more bits ([0104], [0105], memory resources are disabled by programming using patterns and in test mode, memory resources are not used to perform standard memory operations as claimed).
As per claim 4, Park discloses the memory device of claim 1, wherein the one or more memory resources correspond to one or more rows of the memory device ([0059], memory cell has corresponding rows and columns).
As per claim 8, Park discloses a system, comprising: a host device comprising one or more hardware components that are configured to: transmit, to a memory device, a command to write one or more bits to a mode register of the memory device to indicate one or more memory resources of the memory device for performing a memory built-in self-test; (Fig. 2, [0076], [0077], MRS program (writes) various modes of the memory) and the memory device, comprising one or more hardware components or a controller to:
read the one or more bits from the mode register of the memory device before performing the memory built-in self-test; and (Fig. 1, 2, [0076], The control circuit 124 may include a mode register MRS providing a plurality of operational options of the memory device 120 and a test mode register TMRS providing test operational options. An MRS/TMRS 212 may program various functions, characteristics, and modes of the memory device 120. Test mode options (e.g., a DDR test mode or a PBT test mode) to be performed by the MBIST circuit 126, may be selectively set by the MRS/TMRS 212 );
perform the memory built-in self-test using the one or more memory resources of the memory device (Fig. 2, 3, [0094], Referring to FIGS. 2 and 3, an MBIST option may be set in operation S310 and, according to set MBIST option, a PBT test may be performed by the MBIST circuit 126 in operation S320 or a DDR test may be performed by the MBIST circuit 126 in operation S330.).
As per claim 9, Park discloses the system of claim 8, wherein the one or more memory resources are addressable memory resources ([0059], memory controller access memory device and physical address is provided to access the memory).
As per claim 10, Park discloses the system of claim 9, wherein the one or more memory resources are no longer addressable based on the one or more bits ([0104], [0105], memory resources are disabled by programming using patterns).
As per claim 12, Park discloses the system of claim 8, wherein the one or more bits are included in a plurality of bits indicated by the command and read from the mode register of the memory device (Fig. 3, [0094], MBIST option set by programming MRS).
As per claim 18, Park discloses the method of claim 16, wherein the mode register of the memory device includes one or more other bits indicating whether the memory built-in self-test is enabled ([0014], [0076], [0077], setting patterns in enable state indicates MBIST is enabled).
As per claim 19, Park discloses the method of claim 18, wherein the one or more other bits further indicate whether an error-correcting code is enabled for the memory built-in self-test ([0141], MRS setting error correction code (ECC) function).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 5-7, 13-14, 17 are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Nale (US 2020/0176072).
As per claim 5, Park does not specifically disclose the memory device of claim 1, wherein the one or more bits are indicative of a quantity of memory resources of the memory device that are associated with performing the memory built-in self-test;
However, Nale discloses the one or more bits are indicative of a quantity of memory resources of the memory device that are associated with performing the memory built-in self-test ([0031]-[0034]).
Therefore it would have been obvious to the one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate teaching of Nale’s DRAM BIST power fail mitigation system into Park’s method of testing a memory device, a MBIST circuit because one of the ordinary skill in the art would have been motivated to improve reliability and reducing test time.
As per claim 6, Park does not specifically disclose the memory device of claim 1, wherein the one or more hardware components or a controller are configured to perform the memory built-in self-test using one or more other memory resources of the memory device that are configured only for performing the memory built-in self-test;
However, Nale discloses the one or more hardware components or a controller are configured to perform the memory built-in self-test using one or more other memory resources of the memory device that are configured only for performing the memory built-in self-test ([0031], [0033], [0036], 0037]).
Therefore it would have been obvious to the one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate teaching of Nale’s DRAM BIST power fail mitigation system into Park’s method of testing a memory device, a MBIST circuit because one of the ordinary skill in the art would have been motivated to improve reliability and reducing test time.
As per claim 7, Park does not specifically disclose the memory device of claim 1, wherein the one or more hardware components or a controller are configured to perform the memory built-in self-test for one or more memory sections of the memory device that do not include the one or more memory resources;
However, Nale discloses the one or more hardware components or a controller are configured to perform the memory built-in self-test for one or more memory sections of the memory device that do not include the one or more memory resources ([0032], [0034], [0036]).
Therefore it would have been obvious to the one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate teaching of Nale’s DRAM BIST power fail mitigation system into Park’s method of testing a memory device, a MBIST circuit because one of the ordinary skill in the art would have been motivated to improve reliability and reducing test time.
As per claim 13, Park does not specifically disclose the system of claim 12, wherein the plurality of bits includes at least a first bit that corresponds to a first memory section of the memory device and a second bit that corresponds to a second memory section of the memory device;
However, Nale discloses the plurality of bits includes at least a first bit that corresponds to a first memory section of the memory device and a second bit that corresponds to a second memory section of the memory device ([0025]-[0026]);
Therefore it would have been obvious to the one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate teaching of Nale’s DRAM BIST power fail mitigation system into Park’s method of testing a memory device, a MBIST circuit because one of the ordinary skill in the art would have been motivated to improve reliability and reducing test time.
As per claim 14, Park discloses the system of claim 13, wherein the second memory section includes the first memory section and one or more other memory sections ([0025]-[0026]).
As per claim 17, Park does not specifically disclose the method of claim 16, wherein the one or more rows include an initial set of one or more rows of the memory device or a last set of one or more rows of the memory device;
However, Nale discloses the one or more rows include an initial set of one or more rows of the memory device or a last set of one or more rows of the memory device ([0002], [0025]);
Therefore it would have been obvious to the one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate teaching of Nale’s DRAM BIST power fail mitigation system into Park’s method of testing a memory device, a MBIST circuit because one of the ordinary skill in the art would have been motivated to improve reliability and reducing test time.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Gallgher et al. (US 10,706,950, referred herein after Gallagher).
As per claim 15, Park does not specifically disclose the system of claim 8, wherein one or more hardware components or the controller of the memory device are configured to perform the memory built-in self-test for fewer than all memory sections associated with the memory device;
However, Gallagher discloses one or more hardware components or the controller of the memory device are configured to perform the memory built-in self-test for fewer than all memory sections associated with the memory device (Col. 4, lines 9-31, Col. 6, lines 11-28);
Therefore it would have been obvious to the one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate teaching of Gallagher’s testing for memory error correction code logic into Park’s method of testing a memory device, a MBIST circuit because one of the ordinary skill in the art would have been motivated to provide improved testing of memory error correction code (“ECC”) logic with memory built-in self-test (“MBIST”).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Fischer et al. (US 2010/0157703, referred herein after Fishcher).
As per claim 20, Park does not specifically disclose the method of claim 16, wherein the mode register of the memory device includes one or more other bits indicating whether a repair mode of the memory device is enabled;
However, Fischer discloses the mode register of the memory device includes one or more other bits indicating whether a repair mode of the memory device is enabled ([0038]-[0040]);
Therefore it would have been obvious to the one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate teaching of Fischer’s embedded memory repair method into Park’s method of testing a memory device, a MBIST circuit because one of the ordinary skill in the art would have been motivated to provide improved testing of memory error correction code (“ECC”) logic with memory built-in self-test (“MBIST”).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAMINI B PATEL whose telephone number is (571)270-3902. The examiner can normally be reached on M-F 8-4:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ashish Thomas can be reached on 571-272-0631. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KAMINI B PATEL/Primary Examiner, Art Unit 2114