Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4, 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka et al. (US 2004/0027502) in view of Jeon (US 2003/0117536).
Regarding claim 1, Tanaka et al. (figures 23a-23b) discloses an electronic device having a peripheral area, comprising:
a substrate (1);
a first conductive line (24, 200, and 18) disposed on the substrate in the peripheral area and comprising a first section and a second section electrically connected to the first section; and
a first conductive layer (43) disposed on the first section and the second section, wherein the first section is electrically connected to the second section through the first conductive layer, wherein the first conductive layer is electrically connected to the first section through a first contact via, and the first conductive layer is electrically connected to the second section through a second contact via, wherein the first contact via is different from the second contact via (98), wherein in a top view of the electronic device, the first conductive layer (43) is disposed between the first section and the second section along a first direction (horizontal direction or vertical direction), wherein in the top view, the first section has a first minimum width outside the first conductive layer along a second direction perpendicular to the first direction, the first minimum width is measured at a plane where the width of the first section changes (24), the second section has a second minimum width outside the first conductive layer along the second direction, the second minimum width is measured at a plane where the width of the second section changes (18), and the first minimum width is different from the second minimum width (the width of 18 is different from the width of 24).
Tanaka et al. discloses the limitations as shown in the rejection of claim 1 above. However, Tanaka et al. is silent regarding wherein the first conductive layer, the first section and the second section overlap with each other. Jeon (figures 1-4) teaches wherein the first conductive layer, the first section and the second section overlap with each other (6, 2b, 20 and 24). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify connections as taught by Jeon et al. in order to secure the connections between the lines and prevent corrosion of the signal line.
Regarding claim 2, Jeon (figures 1-4) discloses wherein the first section has a third minimum width in the first conductive layer, the second section has a fourth minimum width in the first conductive layer, the third minimum width is greater than the first minimum width, and the fourth minimum width is greater than the second minimum width (6, 2b and 20).
Regarding claim 4, Jeon (figures 1-4) discloses wherein the third minimum width and the fourth minimum width are different (6, 2b and 20).
Regarding claim 6, Jeon (figures 1-4) discloses a second conductive line adjacent to the first conductive line, and a second conductive layer adjacent to the first conductive layer.
Regarding claim 7, Jeon (figures 1-4) discloses wherein the first section has a first edge and a second edge opposite to the first edge, the first minimum width is a shortest distance between the first edge and the second edge along a direction perpendicular to the first edge, the second section has a third edge and a fourth edge opposite to the third edge, the second minimum width is a shortest distance between the third edge and the fourth edge along a direction perpendicular to the third edge.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAUREN NGUYEN whose telephone number is (571)270-1428. The examiner can normally be reached on Monday - Thursday, 8:00 AM -6:00 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jennifer Carruth, can be reached at 571-272-9791. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/LAUREN NGUYEN/Primary Examiner, Art Unit 2871
Prosecution Insights