Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/17/2024 and 04/21/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
5. The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Drawings
6. Figure 1 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
7. Claim 5 - 8 and 16 objected to because of the following informalities:
Claims 5 and 6 line 3 recites “… with the DC link capacitor,”. However, it seems that it should recite “… with a DC link capacitor,”.
Claim 7 recites “…wherein the determining, by the at least one processor, of the length of the non-conducting interval of the switch comprises performing, by the at least one processor, control to decrease…”. However, it appears that it should recite “…wherein the determining, by the at least one processor, of the length of the non-conducting interval of the switch comprises , control to decrease…”.
Claim 8 line 2 recites “…the obtained harmonic component is third-order, fifth-order, …, and Nth-order…”. However, it appears that it should recite “the obtained harmonic component includes all odd harmonics from 3rd-order through Nth-order, where N is an odd integer greater than or equal to 7”.
Claim 16 lines 1 - 2 recites “An electrical appliance configured to operate with minimized operating losses, the home appliance comprising:…”. However it appears that it should recite “An electrical appliance configured to operate with minimized operating losses, the electrical appliance comprising…:.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
8. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
9. Claim(s) 1 - 2, 4, 7 and 11 - 20 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Keller et al (US Pub. No. 2024/0154521 A1); (hereinafter Keller et al).
Regarding claim 1, Keller et al [e.g., Figs. 2 - 5] discloses a home appliance configured to control a harmonic magnitude [e.g., controlling harmonics in output for electronic appliances, p. 0006 recites “Regulators have attempted to control and limit the undesired consequences of line-frequency harmonics on the AC power grid and, accordingly, regulatory requirements have been stipulated. The IEC61000-3-2 international standard, for example, stipulates the maximum permissible amplitudes of line-frequency harmonics up to the 39th harmonic. This requirement applies to most electrical appliances having an input power of 75 W (Class D equipment) or greater. The number and magnitude of harmonics present in the supply current may be compared with the sinusoidal AC input voltage and may be referred to as power factor. …. A power factor of less than one indicates that the voltage and current are not in phase or that the current is not sinusoidal, respectively.”], the home appliance comprising: a current sensor configured to detect an input current from a power source [e.g., current sensing means 224]; and at least one processor [e.g., analyzer circuit 226, control circuit 228 and power factor controller 214 contained within PFC circuit 200] configured to: obtain a harmonic component from the input current detected by the current sensor [e.g., analyzer circuit 226 obtains harmonics of input, p. 0046 recites “In other words, analyzer circuit 226 determines the harmonics of the inductor current waveform in relation to the waveform of the rectified AC voltage.”], determine a length of a non-conducting interval of a switch [e.g., determines components of signal S2 including deadtime β, -- refer to Fig. 3 for timing diagram --, p. 0049 recites “FIG. 3 b) shows a first exemplary input current waveform that may be achieved by applying a corresponding second input signal S2 to the PFC circuit. As is readily visible in the figure, the waveform has a first section α which starts at the zero crossing of the sine wave and may have a variable length. During the first section β of the waveform the input current may be zero. In order to achieve zero input current, the boost switch may be inhibited.”] so that a magnitude of the obtained harmonic component is less than a predetermined harmonic reference value [e.g., signal S2 is generated to control switch 212 when harmonics obtained do not comply with harmonics stipulated in the IEC61000-3-2 standard or comparable standards, p. 0059 recites “In step 106a the input current to the inductor 208 is sampled, and in step 106b an FFT analysis on the sampled current is performed. In step 106c the harmonics of the input current are compared against the regulatory limits, e.g., against the values for harmonics stipulated in the IEC61000-3-2 standard or comparable standards. In step 106d the critical harmonics, i.e., those harmonics that exceed the maximum permissible values are determined and evaluated, and in step 106e the control signal S2 is selected, adapted or modified targeting to bring those harmonics that exceeded the maximum permissible values below those values. Control signal S2 is then applied to the power factor controller 214, which operates the boost switch 212 targeting to cause an input current flow that, while not being a scaled version of the AC input voltage, has harmonics that stay below the regulatory maximum values.”], and generate a current reference value corresponding to the determined length of the non-conducting interval [e.g., -- refer to Fig. 3 for timing diagram --, signal corresponding to α (first section), β (deadtime or lead-up section) and amplitudes η1, η2, p. 0053 recites “The amplitudes η1, η2 of the two sinusoidal parts and the durations of the first section α as well as the lead-up time β may be determined depending on the targeted amount of harmonics and the energy that needs to be transferred during one cycle.”].
Regarding claim 2, Keller et al [e.g., Figs. 2 - 5] discloses a rectifier configured to rectify the input current of the power source [e.g., input rectifier 204]; and a direct current (DC) link capacitor configured to establish a DC voltage output from the rectifier [e.g., output capacitor 218], wherein a magnitude of a DC voltage across the DC link capacitor is greater than a magnitude of an input voltage of the power source [e.g., p. 0049 recites “As some energy is still stored in output capacitor 218, i.e., output capacitor 218 still holds a non-zero voltage, and the momentary AC voltage at the input of the PFC circuit is lower than the non-zero voltage of the output capacitor 218, no current flows through boost rectifier 210, and consequently through input rectifier 204”].
Regarding claim 4, Keller et al [e.g., Figs. 2 - 5 ] discloses wherein the at least one processor [e.g., analyzer circuit 226, control circuit 228 and power factor controller 214 contained within PFC circuit 200] is further configured to generate a pulse width modulation (PWM) switching signal based on the current reference value [e.g., PWM generated by PFC controller circuit 214 to boost switch 212 based on signal S2].
Regarding claim 7, Keller et al [e.g., Figs. 2 - 5 ] discloses wherein the determining, by the at least one processor, of the length of the non-conducting interval of the switch comprises [e.g., determining components of signal S2 by analyzer circuit 226, control circuit 228 and power factor controller 214 contained within PFC circuit 200], control to decrease the length of the non-conducting interval [e.g., controls length of deadtime β depending on the targeted amount of harmonics] when the magnitude of the obtained harmonic component is greater than the predetermined harmonic reference value [e.g., signal S2 is generated as a result of obtained harmonics exceeding harmonics stipulated in the IEC61000-3-2 standard or comparable standards, p. 0059 recites “In step 106c the harmonics of the input current are compared against the regulatory limits, e.g., against the values for harmonics stipulated in the IEC61000-3-2 standard or comparable standards. In step 106d the critical harmonics, i.e., those harmonics that exceed the maximum permissible values are determined and evaluated, and in step 106e the control signal S2 is selected, adapted or modified targeting to bring those harmonics that exceeded the maximum permissible values below those values. Control signal S2 is then applied to the power factor controller 214, which operates the boost switch 212 targeting to cause an input current flow that, while not being a scaled version of the AC input voltage, has harmonics that stay below the regulatory maximum values.”] and increase the length of the non-conducting interval when the magnitude of the obtained harmonic component is less than the predetermined harmonic reference value [e.g., increases non conducting period of signal S2 when harmonics comply with harmonics stipulated in the IEC61000-3-2 standard or comparable standards to allow switch 212 be operated based on signal S1 only, p. 0057 recites “As long as no second input signal S2 is received at the PFC circuit, “no”-branch of step 104, the operation of the boost switch 212, in step 108, is controlled in accordance with the first input signal S1 so as to cause a current flow, at the input of the power supply circuit, that has a waveform targeted to correspond to a scaled version of the waveform of the AC input voltage as represented by the first input signal S1.”].
Regarding claim 11, Keller et al [e.g., Figs. 2 - 5] discloses determining, by the at least one processor [e.g., analyzer circuit 226, control circuit 228 and power factor controller 214 contained within PFC circuit 200], the length of the non-conducting interval [e.g., β (deadtime)], based on an output value [e.g., output value supplied by feedback resistor 220] for controlling the magnitude of the obtained harmonic component to be less than the predetermined harmonic reference value [e.g., control harmonics extracted to be less than harmonics stipulated in the IEC61000-3-2 standard or comparable standards] and a phase difference between the input voltage and the input current of the power source [e.g., controls phase difference between input voltage and input current p. 0046 recites “Power factor controller circuit 214 controls or modifies the operation of the boost switch 212 in accordance with the second control signal S2, targeting to cause a current flow, at the input of the PFC circuit, that, during an AC input voltage half-wave having non-zero input current, has a waveform that at least partially or temporarily does not correspond to a scaled version of the waveform of the AC input voltage. The waveform not corresponding to a scaled version of the AC input voltage may take a shape that will, when analyzed together with the remainder of the half wave, in which the waveform of the input current corresponds to a scaled version of the AC input voltage, will have a power factor that lies above regulatory requirements. In other words, the second control signal reduces the power factor from its ideal value of 1 to a lower value that still complies with the regulatory requirements.”].
Regarding claim 12, Keller et al [e.g., Figs. 2 - 5] discloses wherein the generating, by the at least one processor [e.g., analyzer circuit 226, control circuit 228 and power factor controller 214 contained within PFC circuit 200], of a current reference value [e.g., -- refer to Fig. 3 for timing diagram --, signal containing α (first section), β (deadtime or lead-up section) and amplitudes η1, η2, p. 0053 recites “The amplitudes η1, η2 of the two sinusoidal parts and the durations of the first section α as well as the lead-up time β may be determined depending on the targeted amount of harmonics and the energy that needs to be transferred during one cycle.”] corresponding to the determined length of the non-conducting interval comprises outputting, by the at least one processor [e.g., determining components of signal S2 by analyzer circuit 226, control circuit 228 and power factor controller 214 contained within PFC circuit 200], a current shape reference value [e.g., -- refer to Figs. 3b -- , p.0049 recites “FIG. 3 b) shows a first exemplary input current waveform that may be achieved by applying a corresponding second input signal S2 to the PFC circuit.”] corresponding to the current reference value, based on the determined length of the non-conducting interval [e.g., reference current containing η1, η2, α and β (deadtime) generated by control circuit 228 which, p. 0053 recites “The amplitudes η1, η2 of the two sinusoidal parts and the durations of the first section α as well as the lead-up time β may be determined depending on the targeted amount of harmonics and the energy that needs to be transferred during one cycle.”] and the phase difference between the input voltage and the input current of the power source[e.g., controls phase difference between input voltage and input current p. 0006 recites “The number and magnitude of harmonics present in the supply current may be compared with the sinusoidal AC input voltage and may be referred to as power factor. The power factor of an AC electrical power system is defined as the ratio of the real power absorbed by the load to the apparent power flowing in the circuit, and is a dimensionless number in the closed interval of −1 to 1. A power factor of less than one indicates that the voltage and current are not in phase or that the current is not sinusoidal, respectively.”].
Regarding claim 13, Keller et al [e.g., Figs. 2 - 5 ] discloses an output current sensor configured to detect an output current supplied to a load [e.g., current sense resistor 216], wherein the determining, by the at least one processor, of the length of the non- conducting interval of the switch comprises determining, by the at least one processor [e.g., analyzer circuit 226, control circuit 228 and power factor controller 214 contained within PFC circuit 200], the length of the non-conducting interval based on a variation in the output current supplied to the load [e.g., -- refer to Fig. 3 for timing diagram --, determines α (first section), β (deadtime or lead-up section) to reduce harmonic in output, p. 0053 recites “At the end of the lead-up time β the input current rises linearly, similar as shown in FIG. 3 b), where the input current rises linearly after the deadtime β. At the end of the first section α of the input current waveform, i.e., during the second section of the input current waveform, the input current waveform is sinusoidal, like in any known PFC circuit. The amplitudes η1, η2 of the two sinusoidal parts and the durations of the first section α as well as the lead-up time β may be determined depending on the targeted amount of harmonics and the energy that needs to be transferred during one cycle.”].
Regarding claim 14, Keller et al [e.g., Figs. 2 - 5] discloses wherein the at least one processor [e.g., analyzer circuit 226, control circuit 228 and power factor controller 214 contained within PFC circuit 200] is further configured to perform control so that the magnitude of the obtained harmonic component [e.g., harmonics extracted by analyzer 226] is less than the predetermined harmonic reference value [e.g., control extracted harmonics to comply with harmonics stipulated in the IEC61000-3-2 standard or comparable standards, p. 0059 recites “In step 106a the input current to the inductor 208 is sampled, and in step 106b an FFT analysis on the sampled current is performed. In step 106c the harmonics of the input current are compared against the regulatory limits, e.g., against the values for harmonics stipulated in the IEC61000-3-2 standard or comparable standards. In step 106d the critical harmonics, i.e., those harmonics that exceed the maximum permissible values are determined and evaluated, and in step 106e the control signal S2 is selected, adapted or modified targeting to bring those harmonics that exceeded the maximum permissible values below those values. Control signal S2 is then applied to the power factor controller 214, which operates the boost switch 212 targeting to cause an input current flow that, while not being a scaled version of the AC input voltage, has harmonics that stay below the regulatory maximum values.”] and the length of the non-conducting interval of the switch is maximized [e.g., maximizes deadtime β to minimize operation of the boost switch for reducing losses while ensuring zero crossing, p. 0050 recites “The deadtime β, which starts at the zero crossing of the sine wave, may have a variable length. As mentioned above, during the deadtime β the operation of the boost switch is inhibited, thus eliminating the losses associated with operating the boost switch.”].
Regarding claim 15, Keller et al [e.g., Figs. 2 - 5 ] discloses a method, performed by a home appliance, of controlling a harmonic magnitude [e.g., method of controlling harmonic in output for electronic appliance, p. 0006 recites “Regulators have attempted to control and limit the undesired consequences of line-frequency harmonics on the AC power grid and, accordingly, regulatory requirements have been stipulated. The IEC61000-3-2 international standard, for example, stipulates the maximum permissible amplitudes of line-frequency harmonics up to the 39th harmonic. This requirement applies to most electrical appliances having an input power of 75 W (Class D equipment) or greater. The number and magnitude of harmonics present in the supply current may be compared with the sinusoidal AC input voltage and may be referred to as power factor. …. A power factor of less than one indicates that the voltage and current are not in phase or that the current is not sinusoidal, respectively.”], the method comprising: detecting, by a current sensor of the home appliance, an input current of a power source [e.g., current sensing means 224 detecting input current]; obtaining a harmonic component from the input current detected by the current sensor [e.g., analyzer circuit 226 obtaining harmonics components of input, p. 0046 recites “In other words, analyzer circuit 226 determines the harmonics of the inductor current waveform in relation to the waveform of the rectified AC voltage. The analyzer circuit 226 may implement a Fast Fourier Transformation (FFT) or may comprise filter banks or tunable filters.”]; determining a length of a non-conducting interval of a switch [e.g., determines components of signal including deadtime β, -- refer to Fig. 3 for timing diagram --, p. 0049 recites “FIG. 3 b) shows a first exemplary input current waveform that may be achieved by applying a corresponding second input signal S2 to the PFC circuit. As is readily visible in the figure, the waveform has a first section α which starts at the zero crossing of the sine wave and may have a variable length. During the first section β of the waveform the input current may be zero. In order to achieve zero input current, the boost switch may be inhibited.”] so that a magnitude of the obtained harmonic component is less than a predetermined harmonic reference value [e.g., signal S2 is generated to control switch 212 when harmonics obtained do not comply with harmonics stipulated in the IEC61000-3-2 standard or comparable standards, p. 0059 recites “In step 106a the input current to the inductor 208 is sampled, and in step 106b an FFT analysis on the sampled current is performed. In step 106c the harmonics of the input current are compared against the regulatory limits, e.g., against the values for harmonics stipulated in the IEC61000-3-2 standard or comparable standards. In step 106d the critical harmonics, i.e., those harmonics that exceed the maximum permissible values are determined and evaluated, and in step 106e the control signal S2 is selected, adapted or modified targeting to bring those harmonics that exceeded the maximum permissible values below those values. Control signal S2 is then applied to the power factor controller 214, which operates the boost switch 212 targeting to cause an input current flow that, while not being a scaled version of the AC input voltage, has harmonics that stay below the regulatory maximum values.”]; and generating a current reference value corresponding to the determined length of the non-conducting interval [e.g., -- refer to Fig. 3 for timing diagram --, signal containing α (first section), β (deadtime or lead-up section) and amplitudes η1, η2, p. 0053 recites “The amplitudes η1, η2 of the two sinusoidal parts and the durations of the first section α as well as the lead-up time β may be determined depending on the targeted amount of harmonics and the energy that needs to be transferred during one cycle.”]
Regarding claim 16, Keller et al [e.g., Figs. 2 - 5 ] discloses an electrical appliance configured to operate with minimized operating losses [e.g., p. 0025 recites “…, all while controlling the boost switch in such a way that the switching losses and/or the conducting losses in the PFC circuit are lower when compared to operating the boost switch for obtaining a best possible power factor, or lowest possible harmonics.”], the electrical appliance comprising: at least one harmonic extractor [e.g., analyzer circuit 226] configured to extract magnitudes of harmonic components in real time from a power source including the electrical appliance [e.g., analyzer circuit 226 obtains harmonic components from input, p. 0046 recites “…, “In other words, analyzer circuit 226 determines the harmonics of the inductor current waveform in relation to the waveform of the rectified AC voltage.”]; a harmonic controller configured to control the extracted magnitudes of the harmonics to satisfy predetermined standard values [e.g., control circuit 228 control harmonics to satisfy harmonics stipulated in the IEC61000-3-2 standard or comparable standards, p. 0029 recites “The closed-loop control proposed in this embodiment may make better use of the limits for the amount and magnitudes of harmonics stipulated in the regulations, e.g., in IEC 61000-3-2, while reducing the losses in the PFC circuit to the maximum possible. The closed-loop control also allows for better tracking fluctuations or variations in the output load, thereby facilitating staying within the regulatory limits for harmonics.”], and to calculate a length of a non-conducting interval of a switch in a power factor correction (PFC) circuit [e.g., determines components of signal including deadtime β, -- refer to Fig. 3 for timing diagram --, p. 0049 recites “FIG. 3 b) shows a first exemplary input current waveform that may be achieved by applying a corresponding second input signal S2 to the PFC circuit. As is readily visible in the figure, the waveform has a first section α which starts at the zero crossing of the sine wave and may have a variable length. During the first section β of the waveform the input current may be zero. In order to achieve zero input current, the boost switch may be inhibited.”]; and a pulse width modulation (PWM) generator configured to control the switch based on the non-conducting interval [e.g., PWM generated by PFC controller circuit 214 to boost switch 212 based on signal S2].
Regarding claim 17, Keller et al [e.g., Figs. 2 - 5 ] discloses the harmonic controller determines that the extracted magnitudes do not satisfy the predetermined standard values in response to the extracted magnitudes exceeding the predetermined standard values [e.g., control circuit 228 determined that the harmonics extracted are compliant with harmonics stipulated in the IEC61000-3-2 standard or comparable standards, p.0059 recites “In step 106a the input current to the inductor 208 is sampled, and in step 106b an FFT analysis on the sampled current is performed. In step 106c the harmonics of the input current are compared against the regulatory limits, e.g., against the values for harmonics stipulated in the IEC61000-3-2 standard or comparable standards. In step 106d the critical harmonics, i.e., those harmonics that exceed the maximum permissible values are determined and evaluated, and in step 106e the control signal S2 is selected, adapted or modified targeting to bring those harmonics that exceeded the maximum permissible values below those values. Control signal S2 is then applied to the power factor controller 214, which operates the boost switch 212 targeting to cause an input current flow that, while not being a scaled version of the AC input voltage, has harmonics that stay below the regulatory maximum values.”].
Regarding claim 18, Keller et al [e.g., Figs. 2 - 5 ] discloses wherein calculating the length of the non-conducting value [e.g., signal containing β (deadtime)] comprises: calculating a control value [e.g., signal S2] that reduces the length of the non-conducting interval in response to the extracted magnitudes not satisfying the predetermined standard values [e.g., -- refer to Fig. 3b --, controls signal S2 when harmonics exceed harmonics stipulated in the IEC61000-3-2 standard or comparable standards, p. 0059 recites “In step 106c the harmonics of the input current are compared against the regulatory limits, e.g., against the values for harmonics stipulated in the IEC61000-3-2 standard or comparable standards. In step 106d the critical harmonics, i.e., those harmonics that exceed the maximum permissible values are determined and evaluated, and in step 106e the control signal S2 is selected, adapted or modified targeting to bring those harmonics that exceeded the maximum permissible values below those values. Control signal S2 is then applied to the power factor controller 214, which operates the boost switch 212 targeting to cause an input current flow that, while not being a scaled version of the AC input voltage, has harmonics that stay below the regulatory maximum values.”] and calculating a control value that increases the length of a non-conducting interval in response to the extracted magnitudes satisfying the predetermined standard values [e.g., increases non conducting time of signal S2 when harmonics comply with harmonics stipulated in the IEC61000-3-2 standard or comparable standards, p. 0057 recites “As long as no second input signal S2 is received at the PFC circuit, “no”-branch of step 104, the operation of the boost switch 212, in step 108, is controlled in accordance with the first input signal S1 so as to cause a current flow, at the input of the power supply circuit, that has a waveform targeted to correspond to a scaled version of the waveform of the AC input voltage as represented by the first input signal S1.”].
Regarding claim 19, Keller et al [e.g., Figs. 2 - 5 ] discloses a current controller configured to generate a current reference value corresponding to the length of the non-conducting interval [e.g., -- refer to Fig. 3 for timing diagram --, signal corresponding to α (first section), β (deadtime or lead-up section) and amplitudes η1, η2, p. 0053 recites “The amplitudes η1, η2 of the two sinusoidal parts and the durations of the first section α as well as the lead-up time β may be determined depending on the targeted amount of harmonics and the energy that needs to be transferred during one cycle.”]
Regarding claim 20, Keller et al [e.g., Figs. 2 - 5 ] discloses to generate a PWM switching signal that controls the switch based at least in part on the current reference value [e.g., power factor controller 214 controls switching of 212 based in part to second control signal S2].
Claim Rejections - 35 USC § 103
10. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
11. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
12. Claim(s) 3 is rejected under 35 U.S.C. 103 as being unpatentable over Keller et al (US Pub. No. 2024/0154521 A1) in view of Li (US Patent No. 7,359,224 B2); (hereinafter Keller et al and Li).
Regarding claim 3, Keller et al discloses the claimed invention except for a voltage sensor configured to detect the magnitude of the DC voltage across the DC link capacitor, wherein the generating of the current reference value corresponding to the determined length of the non-conducting interval comprises inputting, to a voltage controller, by the at least one processor, a result of comparing the magnitude of the DC voltage detected via the voltage sensor with a DC link voltage reference, inputting, to a current controller, an output of the voltage controller, the length of the non-conducting interval, and the input current obtained from the current sensor, and outputting the current reference value from the current controller.
Li [e.g., Fig. 1A] teaches a voltage sensor configured to detect the magnitude of the DC voltage across the DC link capacitor [e.g., A/D 12 detecting V_DC], wherein the generating of the current reference value comprises inputting, to a voltage controller [e.g., inputting to PI controller 18], a result of comparing the magnitude of the DC voltage detected via the voltage sensor with a DC link voltage reference [e.g., output of difference circuit 16 inputted to PI controller 18 between DC reference voltage (Vdc_Ref) and digitized DC bus voltage (VdcFdb)], inputting, to a current controller [e.g., result inputted PI current regulator 26 via multiplier 22], an output of the voltage controller [e.g., receives output of PI voltage regulator 18 (VAOut)], and the input current obtained from the current sensor [e.g., input current I_IN], and outputting the current reference value from the current controller [e.g., output reference current to comparator 28].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Keller et al with a voltage sensor configured to detect the magnitude of the DC voltage across the DC link capacitor, wherein the generating of the current reference value comprises inputting, to a voltage controller, a result of comparing the magnitude of the DC voltage detected via the voltage sensor with a DC link voltage reference, inputting, to a current controller, an output of the voltage controller, and the input current obtained from the current sensor, and outputting the current reference value from the current controller as suggested by Li to ensure that the AC voltage and current are substantially in phase which improves efficiency and at the same time eliminates the generation of harmful harmonics.
13. Claim(s) 5 - 6 are rejected under 35 U.S.C. 103 as being unpatentable over Keller et al (US Pub. No. 2024/0154521 A1) in view Kim et al US Pub. No. 2023/0155485 A1); (hereinafter Keller et al and Kim et al).
Regarding claim 5, Keller et al discloses the claimed invention except for a power factor correction (PFC) converter having a plurality of legs in parallel with the DC link capacitor, wherein the at least one processor is further configured to randomly select at least one of the plurality of legs, and turn on and off a switch included in the randomly selected at least one leg via the PWM switching signal. Kim et al [e.g., Figs. 1 - 2] teaches a power factor correction (PFC) converter [e.g., p. 0066 recites “…the power transforming apparatus 100 may include a rectifier unit 120 that rectifies the AC power output from the power supply unit 110, reactors 130 that smooth the rectified power, a plurality of converters 140 having power semiconductor devices to perform a PFC operation for improving power factor, a DC link capacitor 150, and an inverter 160, and may be connected to the motor 170 driven by a current supplied from the inverter 160.”] having a plurality of legs in parallel with the DC link capacitor [e.g., plurality of legs of in parallel to DC link capacitor 150], wherein the at least one processor is further configured to randomly select at least one of the plurality of legs [e.g., -- refer to Fig. 2--, controller 250], and turn on and off a switch included in the randomly selected at least one leg via the PWM switching signal [e.g., controls switches of converter 140 randomly, p. 0082 recites “…,the controller 250 may apply a control algorithm such that target converter channels are randomly determined or selected differently each time, even when determining an additional target converter channel or when determining a converter channel to be excluded from the PFC operation in a medium-load or high-load section.”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Keller et al with a power factor correction (PFC) converter having a plurality of legs in parallel with the DC link capacitor, wherein the at least one processor is further configured to randomly select at least one of the plurality of legs, and turn on and off a switch included in the randomly selected at least one leg via the PWM switching signal as suggested by Kim et al for preventing the life of a specific converter switch from being shortened due to continuous stress during operation.
Regarding claim 6, Keller et al discloses the claimed invention except for a power factor correction (PFC) converter having a plurality of legs in parallel with the DC link capacitor, wherein the at least one processor is further configured to sequentially select the plurality of legs, and turn on and off a switch included in at least one leg selected from among the plurality of legs via the PWM switching signal.
Kim et al [e.g., Figs. 1, 2, 6A and 6B] teaches a power factor correction (PFC) converter having a plurality of legs in parallel with the DC link capacitor [e.g., power transforming apparatus 100 containing plurality of legs of in parallel to DC link capacitor 150, p. 0066 recites “…the power transforming apparatus 100 may include a rectifier unit 120 that rectifies the AC power output from the power supply unit 110, reactors 130 that smooth the rectified power, a plurality of converters 140 having power semiconductor devices to perform a PFC operation for improving power factor, a DC link capacitor 150, and an inverter 160, and may be connected to the motor 170 driven by a current supplied from the inverter 160.”], wherein the at least one processor [e.g., controller 250] is further configured to sequentially select the plurality of legs, and turn on and off a switch included in at least one leg selected from among the plurality of legs via the PWM switching signal [e.g., controls plurality of legs sequentially according to the output needed as the load increases/decreases, p. 0136 recites “On the other hand, in FIG. 6B, it has been described as an example in which the number of target converter channels sequentially increases from 1 -> 2 -> 3 and then decreases to 3 -> 2 -> 1, but the present disclosure is of course not limited thereto. For example, subsequent to reaching the first switching boundary point 633, when the input power increases and reaches the second boundary point 632, the PFC operation is performed again with three converter channels.”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Keller et al with a power factor correction (PFC) converter having a plurality of legs in parallel with the DC link capacitor, wherein the at least one processor is further configured to sequentially select the plurality of legs, and turn on and off a switch included in at least one leg selected from among the plurality of legs via the PWM switching signal as suggested by Kim et al to increase/decrease the current capacity of the converter as the output load increases/decreases.
15. Claim(s) 9 is rejected under 35 U.S.C. 103 as being unpatentable over Keller et al (US Pub. No. 2024/0154521 A1) in view of Akira (JP 2020014350A); (hereinafter Keller et al and Akira).
Regarding claim 9, Keller et al discloses the claimed invention except for wherein the obtained harmonic component is a third-order harmonic component and an Nth-order harmonic component where N is an odd integer greater than or equal to 5, and the determining, by the at least one processor, of the length of the non-conducting interval of the switch comprises, when a magnitude of the Nth-order harmonic component is less than a predetermined Nth harmonic reference value, determining, by the at least one processor, the length of the non-conducting interval based on a result of subtracting a magnitude of the third-order harmonic component from a predetermined third harmonic reference value. Akira [e.g., Fig. 1B] teaches wherein the obtained harmonic component is a third-order harmonic component [e.g., harmonic current command ICOM3] and an Nth-order harmonic component where N is an odd integer greater than or equal to 5 [e.g., harmonic current commands ICOM5, ICOM 2n+1…], and the determining, by the at least one processor, of the length of the non-conducting interval of the switch comprises, when a magnitude of the Nth-order harmonic component is less than a predetermined Nth harmonic reference value [e.g., when magnitude of D-axis magnitude of coordinate converter 77 corresponding to harmonic generator 952 supplied to subtractor 78A is less than zero or minute value, Disclosure recites “The second input of the subtractor 78A is supplied with zero or a minute value, and the second input of the subtractor 78B is connected to, for example, the output corresponding to the third harmonic current command ICOM3 of the harmonic current command generator 61B. .”], determining, by the at least one processor, the length of the non-conducting interval based on a result of subtracting a magnitude of the third-order harmonic component from a predetermined third harmonic reference value [e.g., subtracts the output value from the Q-axis output of the orthogonal coordinate converter 77 from the value of the third harmonic current command, Disclosure recites “The subtractor 78B subtracts the output value from the Q-axis output of the orthogonal coordinate converter 77 from the value of the third harmonic current command, which is one of the output values of the harmonic current command generator 61B, and calculates the difference. It is supplied to the input of the harmonic current controller 79B. The harmonic current controller 79B performs, for example, proportional integral control on the output value of the subtractor 78B, so that the Q-axis output of the orthogonal coordinate converter 77 follows the value of the third harmonic current command ICOM3.”.
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Keller et al with wherein the obtained harmonic component is a third-order harmonic component and an Nth-order harmonic component where N is an odd integer greater than or equal to 5, and the determining, by the at least one processor, of the length of the non-conducting interval of the switch comprises, when a magnitude of the Nth-order harmonic component is less than a predetermined Nth harmonic reference value, determining, by the at least one processor, the length of the non-conducting interval based on a result of subtracting a magnitude of the third-order harmonic component from a predetermined third harmonic reference value as suggested by Akira to continuously adjust the third harmonic component based on the following odd harmonic component and generate a harmonic correction command in order to reduce the targeted harmonic component from the output current.
Examiner’s Note
16. Examiner has cited particular columns, paragraphs and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figure may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art disclosed by the Examiner.
17. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Allowable Subject Matter
18. Claims 8 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the indication of the allowability of claim 8 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “…, a minimum value among an output of a third harmonic magnitude controller taking as an input a difference between the third-order harmonics and a third harmonic reference value, an output of a fifth harmonic magnitude controller taking as an input a difference between the fifth- order harmonics and a fifth harmonic reference value, and an output of an Nth harmonic magnitude controller taking as an input a difference between the Nth- order harmonics and an Nth harmonic reference value, and determining the length of the non-conducting interval based on the minimum value.”
The primary reason for the indication of the allowability of claim 10 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “…, when the magnitude of the Nth-order harmonic component is greater than the predetermined Nth harmonic reference value, subtracting, by the at least one processor, from the predetermined third harmonic reference value, an output of a controller that receives as an input a result of subtracting the magnitude of the Nth-order harmonic component from the predetermined Nth harmonic reference value, and determining the length of the non-conducting interval based on a result of subtracting the magnitude of the third-order harmonic component from the third harmonic reference value that is the result of the subtraction.”.
Conclusion
19. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US Pub. No. 2020/0379495 A1 (Wang et al) discloses a power factor correction circuit configured to measure a total harmonic distortion (THD) and an amplitude ratio of each harmonic component.
US Pub. No. 2007/0103947 A1 (Taguchi et al) discloses a power source circuit that converts a commercial power source to a power source such as a home appliance machine.
US Pub. No. 2018/0269779 A1 (Wang et al) discloses a power factor correction circuit can include: a power meter configured to measure THD.
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/ULARISLAO CORDOVA/Examiner, Art Unit 2838
/FRED E FINCH III/Primary Examiner, Art Unit 2838
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