DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The response filed 06/03/2024 is accepted, in which, the specification is amended to include foreign priority of Chinese application 202310678533.4, filed on 09 June 2023. Claims 1 and 11 are independent with claims 1-20 awaiting an action on the merits as follows.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
Claim 20 is objected to for minor informalities.
Regarding claim 20, the claim recites, " exposing by the second recesses." This statement appears to be in incorrect grammatical tense. To further prosecution, Examiner will assume the claim should read, " exposed by the second recesses." Proper correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. —The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected for indefiniteness.
Regarding claim 1, the claim recites, "the semiconductor device." There is insufficient antecedent basis for this element. To further prosecution, Examiner will assume the claim should read, "the packaged semiconductor device." Proper correction is required.
Regarding claim 6, the claim recites, "the recesses region." There is insufficient antecedent basis for this element. To further prosecution, Examiner will assume the recesses region is the area containing the recesses recited in claim 1. Proper correction is required.
Regarding claim 9, the claim recites, "the exposed side-face." There is insufficient antecedent basis for this element. to further prosecution, Examiner will assume claim 9 is referring to the side-face in claim 2. Proper correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-9, 11, 14, and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fogelson (US 6608366 B1).
Regarding claim 1, Fogelson teaches a packaged semiconductor device (40, Fig 7) having a first surface (44), a second surface (46, Fig 8) opposite (shown opposite) the first surface (44), and sidewalls (50) therebetween (shown between), wherein the semiconductor device (40) comprising:
a device die (chip: semiconductor chip, not shown; semiconductor chip attached to die pad, [Claim 4]) arranged in a central region (18A: central region of die pad) surrounded (shown surrounded) by the sidewalls (50);
a plurality of electrically conductive contacts (20) around (shown around) a peripheral region of the second surface (46); and
molding compound (42) between (shown between) electrically conductive contacts (20), and between (shown between) the device die (chip) and the electrically conductive contacts (20);
wherein the electrically conductive contacts (20) each have an end side surface (20A: end side surfaced exposed at sidewall 50) forming (shown forming) a part of the sidewall (50), and
remainder of the sidewall (50) comprises surfaces of the molding compound (42); and
wherein the packaged semiconductor device (40) has recesses (16, Fig 1) between (shown between) the electrically conductive contacts (20),
each recess (16) has a first distance (D1: half the height from bottom surface of 20 to top surface of 20, Fig 9) along the sidewall (50) from the second surface (46) towards the first surface (44), and a second distance (D2: horizontal distance from sidewall 50 to 40% of the length of contact 20, Fig 8) from the sidewall (50) towards the central region (18A).
Regarding claim 2, Fogelson teaches the device of claim 1 and goes on to teach wherein the recesses (16, Fig 1) expose (shown exposed) a part of a side-face (20B: side surface of 20 running from end surface 20A to end surface 22) of the electrically conductive contacts (20).
Regarding claim 3, Fogelson teaches the device of claim 1 and goes on to teach wherein the molding compound (42, Fig 7) is exposed (shown exposed) on the first surface (44) of the packaged semiconductor device (40).
Regarding claim 4, Fogelson teaches the device of claim 1 and goes on to teach wherein electrically conductive contacts (20, Fig 8) extend a third distance (D3: horizontal length of 20 from sidewall 50 to internal end surface 22 shown in Fig 1) from the sidewalls (50) towards the central region (18A), and
the second distance (D2) is between (shown between) 25% and 50% (40%) of the third distance (D3).
Regarding claim 5, Fogelson teaches the device of claim 1 and goes on to teach wherein the electrically conductive contacts (20, Fig 9) extend a fourth distance (D4: maximum height of 20) along the sidewalls (50) from the second surface (46) towards the first surface (44), and
the first distance (D1) is between (shown between) 40% and 60% (50%) of the fourth distance (D4).
Regarding claim 6, Fogelson teaches the device of claim 1 and goes on to teach wherein the device die (chip, not shown) is arranged on (semiconductor chip attached to die pad, [Claim 4]) a die flag (18, Fig 8) in (shown in) the central region (18A), and wherein
at least one of a perimeter region of the die flag (18) and an innermost end region of the electrically conductive contacts (20) is recessed (shown recessed) from the second surface (46), and wherein
the recesses region (16A: area containing recesses 16) from the second surface (46) comprises the molding compound (42).
Regarding claim 7, Fogelson teaches the device of claim 1 and goes on to teach wherein the electrically conductive contacts (20, Fig 1) each comprise a plated material (34A: plating layer shown as hashed layer in Fig 5; plated surfaces, [Col 2, Ln 24-25]) at the second surface (46).
Regarding claim 8, Fogelson teaches the device of claim 1 and goes on to teach wherein the end side surfaces (20A, Fig 11) of the electrically conductive contacts (20) each comprise a plated material (34A: plating layer shown as hashed layer in Fig 5; plated surfaces, [Col 2, Ln 24-25]).
Regarding claim 9, Fogelson teaches the device of claim 8 and goes on to teach wherein the exposed side-face (20B, Fig 1) of the electrically conductive contacts (20), and a part of the end side surface (20A), each comprise a plated material (34A: plating layer shown as hashed layer in Fig 5; plated surfaces, [Col 2, Ln 24-25]).
Regarding claim 11, Fogelson teaches a method of manufacturing a packaged semiconductor device (40, Fig 7) comprising:
providing an array of lead-frames (10, Fig 1) comprising at least two lead-frames (12) and a connection bar (S) therebetween (shown between), wherein
each lead-frame (12) is connected (shown connected) to a respective side of the connection bar (S), wherein
each lead-frame (12) comprises a plurality of electrically conductive contacts (20) connected (shown connected) to and along (shown along) the side of the connection bar (S) to which said lead-frame (12) is connected, and wherein
the connection bar (S) further comprises outer parts (S1: outer parts of S along dotted line connecting to outermost end parts 20A) between (shown between) and connecting (shown connecting) outermost end parts (20A: end side surfaced exposed at sidewall 50, Fig 7) of the electrically conductive contacts (20),
the outer parts (S1) having first recesses (16A: horizontal portions of recesses 16, Fig 1) between (shown between) adjacent electrically conductive contacts (20), such that a first thickness (T1: thickness of 0 where S1 portion includes the end portion of 16) of the outer part (S1) is less (shown less) than a full thickness (T2: maximum total thickness of 20, from bottom surface 28 shown in Fig 1 to top surface 26 shown in Fig 2) of the lead-frame (12);
disposing molding compound (42, Fig 7) in the first recesses (16A) from a first side-face (26) of the connection bar (S);
removing (cut apart, [Col 1, Ln 58-59]) a remainder part (S1A: remainder of S1) of the outer parts (S1) having the first thickness (T1) from the second side-face (28) of the connection bar (S) opposite (shown opposite) the first side-face (26), such that the outer parts (S1) have second recesses (34, Fig 7) on the second side-face (28); and
separating (cut apart, [Col 1, Ln 58-59]) the connection bar (S) from the electrically conductive contacts (20) to produce the packaged semiconductor device (40),
the packaged semiconductor device (40) has the second recesses (34) between (shown between) the electrically conductive contacts (20).
Regarding claim 14, Fogelson teaches the method of claim 11 and goes on to teach further comprising encapsulating (encapsulating, [Claim 4]) a device die (chip: semiconductor chip, not shown; semiconductor chip attached to die pad, [Claim 4]) assembled to the array of lead-frames (10) with the molding compound (42),
including disposing molding compound (42) in (shown in) the first recesses (16A) from the first side-face (26) of the connection bar (S), and
exposing (shown exposed, Fig 8) the second side-face (28) of the electrically conductive contacts (20) opposite (shown opposite) the first side-face (26).
Regarding claim 19, Fogelson teaches the method of claim 11 and goes on to teach wherein the second recesses (34, Fig 9) expose (shown exposed) a part of a side-face (20I: side face of 20 along recess 34) of the electrically conductive contacts (20).
Regarding claim 20, Fogelson teaches the method of claim 19 and goes on to teach further comprising plating (34A: plating layer shown as hashed layer in Fig 5; plated surfaces, [Col 2, Ln 24-25]) the part of the side-face (20I) of the electrically conductive contacts (20) exposing (shown exposed) by the second recesses (34).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Fogelson (US 6608366 B1) as applied to claims 1-9 above, and further in view of Liew (US 20230117260 A1).
Regarding claim 10, Fogelson teaches the device of claim 1 and the first distance (D1, Fig 9).
Fogelson fails to explicitly teach the first distance is between 0.05 and 0.13 millimeters.
However, Liew teaches the recessed cavities may have a depth of about 25% to 75% of lead frame (Liew, [0045]).
MPEP 2144.04 Section IV.B states that limitations related to changes in shape are not sufficient to patentably distinguish over the prior art. A person of ordinary skill in the art would have found it obvious to change the shape of a non-critical element.
In cases like the present, where patentability is said to be based upon particular chosen dimensions or upon another variable recited within the claims, applicant must show that the chosen dimensions are critical. While paragraph [0027] of the instant application's specification states, "… the first half-depth recess 416 can be implemented to a depth of between 0.05 and 0.15 millimeters, and may be even deeper to 0.2mm;" the specification is silent as to the criticality of this dimension of the recess.
As such, the claimed dimensions appear to be an obvious matter of engineering design choice and thus, while being a difference, does not serve in any way to patentably distinguish the claimed invention from the applied prior art. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990); In re Kuhle, 526 F2d. 553, 555, 188 USPQ 7, 9 (CCPA 1975).
One of ordinary skill in the art would have found it obvious to combine Fogelson with Liew to create the packaged semiconductor device of claim 1, wherein the first distance is between 0.05 and 0.13 millimeters.
Fogelson and Liew are considered analogous to the claimed invention because both are from the same field of endeavor of packaged semiconductor devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Fogelson with the features of Liew to create the packaged semiconductor device of claim 1, wherein the first distance is between 0.05 and 0.13 millimeters to protect semiconductor devices during operation; to provide for enhanced heat removal (Liew, [0003]); and to help reduce the delamination between mold compound and the lead frame (Liew, [0010]); because forming the recessed cavities in the tie bars of the lead frame blank may reduce the amount of metal that is removed during a sawing operation, which may reduce a level of mechanical and/or thermal stress imparted to the package during singulation (Liew, [0042]).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Fogelson (US 6608366 B1), and further in view of Lohia (US 20150262903 A1).
Regarding claim 12, Fogelson teaches the method of claim 11, the array of lead-frames (12, Fig 1), the outer parts (S1) of the connection bar (S), the first side-face (26), the adjacent electrically conductive contacts (20), the connection bar (S), and the first recesses (16A).
Fogelson fails to explicitly teach providing the array of lead-frames comprises etching the outer parts of the connection bar on the first side-face at locations between the adjacent electrically conductive contacts to provide the connection bar with the first recesses.
However, Lohia teaches wherein providing the array of lead-frames comprises etching (etching, [0021]) the outer parts of the connection bar on (on, etching would be done from the top) the first side-face at locations between (shown between) the adjacent electrically conductive contacts to provide the connection bar with the first recesses.
Fogelson and Lohia are considered analogous to the claimed invention because both are from the same field of endeavor of packaged semiconductor devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Fogelson with the features of Lohia to create a method wherein providing the array of lead-frames comprises etching the outer parts of the connection bar on the first side-face at locations between the adjacent electrically conductive contacts to provide the connection bar with the first recesses because etching sheet metal to fabricate the connection bar is low cost and allows for batch processing (Lohia, [0021]) to create a device that mitigates stress and reduces microcracks in solder joints (Lohia, [0007]).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Fogelson (US 6608366 B1), in view of Lohia (US 20150262903 A1), and further in view of Liew (US 20230117260 A1).
Regarding claim 13, the combination of Fogelson and Lohia discloses the method of claim 12. Fogelson teaches the outer parts (S1, Fig 1) of the connection bar (S), the first side-face (26), and the full thickness (T2) of the lead-frame (12).
The combination fails to explicitly teach etching the outer parts of the connection bar on the first side-face comprising etching outer parts of the connection bar from the first side-face until a distance between 40% and 60% of the full thickness of the lead-frame.
However, Liew teaches wherein etching the outer parts of the connection bar on the first side-face comprising etching outer parts (133, Fig 2) of the connection bar from (shown etching from first side surface, Fig 3B) the first side-face until a distance (50%, [0045]) between (shown between) 40% and 60% of the full thickness of the lead-frame.
Fogelson, Lohia, and Liew are considered analogous to the claimed invention because all are from the same field of endeavor of packaged semiconductor devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Fogelson and Lohia with the features of Liew to create a method wherein etching the outer parts of the connection bar on the first side-face comprising etching outer parts of the connection bar from the first side-face until a distance between 40% and 60% of the full thickness of the lead-frame to protect semiconductor devices during operation; to provide for enhanced heat removal (Liew, [0003]); and to help reduce the delamination between mold compound and the lead frame (Liew, [0010]); because forming the recessed cavities in the tie bars of the lead frame blank may reduce the amount of metal that is removed during a sawing operation, which may reduce a level of mechanical and/or thermal stress imparted to the package during singulation (Liew, [0042]).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Fogelson (US 6608366 B1), and further in view of Bae (US 8866278 B1).
Regarding claim 15, Fogelson teaches the method of claim 11, the remainder part (S1A) of the outer parts (S1, Fig 1), the second side-face (28), the molding compound (42), and the first recess (16A).
Fogelson fails to explicitly teach removing the remainder part of the outer parts comprise etching the outer parts on the second side-face until the molding compound in the first recess.
However, Bae teaches wherein removing (removal of connectors, [Col 9, Ln 20-23]) the remainder part of the outer parts comprise etching (etching outer parts 123, [Col 9, Ln 23]) the outer parts on (shown on the second side face to form 160a until molding compound 160) the second side-face until (shown until) the molding compound in the first recess.
Fogelson and Bae are considered analogous to the claimed invention because both are from the same field of endeavor of packaged semiconductor devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Fogelson with the features of Bae to create a method wherein removing the remainder part of the outer parts comprise etching the outer parts on the second side-face until the molding compound in the first recess to form a device that includes an increased number of lands serving as I/O's (Bae, [Col 1, Ln 19-20]) with increased functional capacity, coupled with reduced size and weight (Bae, [Col 1, Ln 65]) which may be fabricated in accordance with standard, low-cost forming techniques Bae, [Col 2, Ln 9-10]).
Claim 16-18 rejected under 35 U.S.C. 103 as being unpatentable over Fogelson (US 6608366 B1), and further in view of Talledo (US 20200194351 A1).
Regarding claim 16, Fogelson teaches the method of claim 11, the molding compound (42), and goes on to teach wherein each electrically conductive contact (20, Fig 1) comprises an innermost end region (22) close (shown close, Fig 1) to a central region of the lead-frame (12), and
has a first side-face (24T: top side surface of 20) and an opposite second side-face (24B: bottom side surface of 20).
Fogelson fails to explicitly teach the electrically conductive contact has a third recess at the innermost end region, the third recess receives the molding compound.
However, Talledo teaches the electrically conductive contact has a third recess (18A: recess etched above lead 18, Fig 3) at the innermost end region,
the third recess (18A) receives (shown receiving) the molding compound.
Fogelson and Talledo are considered analogous to the claimed invention because both are from the same field of endeavor of packaged semiconductor devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Fogelson with the features of Talledo to create a method wherein the electrically conductive contact has a third recess at the innermost end region, the third recess receives the molding compound to reduce the size of the package, while maintaining minimum specifications, such as distances between electrical components in the package to prevent short circuiting or other electrical failures, as well as suitable sized lands for soldering the package to the PCB (Talledo, [0003]). The lead locks and the protrusions in the die pad aid in locking the leads and the die pad in the encapsulation material (Talledo, [0004]).
Regarding claim 17, the combination of Fogelson and Talledo discloses the method of claim 16. Fogelson teaches the array of lead-frames (10, Fig 1), the innermost end (22) of the electrically conductive contact (20), and the second side-face (28) of the connection bar (S).
Talledo goes on to teach wherein providing the array of lead-frames comprises etching (etching, [0031]) a second side-face (55, Fig 3) of the innermost end of the electrically conductive contact to provide the third recess,
the second side-face (55) of the innermost end of the electrically conductive contact is coplanar (shown coplanar with the bottom which is the second side surface of the connection bar S of Fogelson) with the second side-face of the connection bar.
Regarding claim 18, the combination of Fogelson and Talledo discloses the method of claim 16. Talledo teaches the third recess (18A, Fig 3).
Fogelson goes on to teach further comprising encapsulating (encapsulating, [Claim 4]) a respective device die (chip: semiconductor chip, not shown; semiconductor chip attached to die pad, [Claim 4]) assembled to a one of the array of lead-frames (12) with the molding compound (42),
including disposing (disposing; when combined with Talledo, the molding compound of Fogelson would flow into the third recess of Talledo) the molding compound (42) in the third recess.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yow (US 20140264793 A1) - Lead frame with stress relief
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jeremy D Watts whose telephone number is (703)756-1055. The examiner can normally be reached M-R 8:00am-4:30pm, F 8:00-3pm EST.
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/JEREMY DANIEL WATTS/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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