Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 21, 26, 27, 32-34 and 37-42 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 5-7, 11, 15, 16 and 19-24 of U.S. Patent No. 12,003,222. Although the claims at issue are not identical, they are not patentably distinct from each other because all claimed limitations are present/inherent in the patent.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 21, 28 and 29 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by CHAWLA (20210092540).
Regarding claim 21, CHAWLA (Figs. 1, 2, and 5) discloses a circuit comprising: a modulation circuit (102) having a first input (Audio_P), a second input (Audio_N), see Figure 5, a first modulated signal output (B), and a second modulated signal output (A); a first multiplexer (507) having inputs coupled to the first and second modulated signal outputs (B and A); a second multiplexer (508) having inputs coupled to the first and second modulated signal outputs (B and A); see Figure 2, a first power stage (202, 206) having a first power stage input (P) and a first power stage output (222), the first power stage input (P) coupled to an output of the first multiplexer (P); and a second power stage (204, 208) having a second power stage input (N) and a second power stage output (224), the second power stage input (N) coupled to an output of the second multiplexer (N).
Regarding claim 28, wherein the first power stage includes a first transistor (202) coupled between a power terminal (210) and the first power stage output (222), and a second transistor (206) coupled between the first power stage output (222) and a reference terminal (212), the first and second transistors having control terminals coupled to the first power stage input (P); and wherein the second power stage includes a third transistor (204) coupled between the power terminal (210) and the second power stage output (224), and a fourth transistor (208) coupled between the second power stage output (224) and the reference terminal (212), the third and fourth transistors having control terminals coupled to the second power stage input (N).
Regarding claim 29, see Fig. 5), wherein the modulator circuit includes a first comparator (501) coupled between the first input (Audio_P_DC) and the first modulated signal output (B) and a second comparator (502) coupled between the second input (Audio_N_DC) and the second modulated signal output (A).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 30 and 31 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHAWLA in view of Coyne (10,862,471).
Regarding claim 30, CHAWLA discloses claimed invention except having loop filter as claimed, see above. Coyne (Fig. 1) discloses a circuit comprising loop filter (105) having inputs (in_n and in_p) and outputs (m_in_n and m_in_p) respectively connected to inputs of modulator (110). Accordingly, it would have been obvious in view of the reference, taken as a whole, to have modified the circuit CHAWLA to have included a loop filter to respective inputs of the modulator, as taught by Coyne. Such a modification would have imparted the advantageous benefit of improved noise, see column 4, lines 19-23 as taught by Coyne, to CHAWLA reference, thereby suggesting the obviousness of such a modification.
Regarding claim 31, Coyne discloses the loop filter and no details shown comprises “a first resistor coupled between a first audio input and a first filter input; a second resistor coupled between a second audio input and a second filter input; a third resistor coupled between the first filter input and the first power stage output; and a fourth resistor coupled between the second filter input and the second power stage output”. However, this specific structure of the loop filter is well-known in the art, see Lesso (20130127531), (Fig. 4) and thus would have been obvious to a person having ordinary skills in the art to utilize such a well-known loop filter.
Allowable Subject Matter
Claims 22-25, 35 and 36 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 22-25, prior art(s) does not disclose the first multiplexer has a first selection input, the second multiplexer has a second selection input, and the apparatus further comprises a selection circuit having inputs coupled to the first and second power stage outputs, and an output of the selection circuit coupled to the first and second selection inputs.
Regarding claim 35, prior art(s) does not disclose the mode detector has a detector input coupled to one of the first or second power stages, and the mode detector configured to detect the idle mode based on a pulse width of a signal at the one of the first or second power stage outputs exceeding a threshold.
Regarding claim 36, prior art(s) does not disclose the first input is coupled to a first audio input, the second input is coupled to a second audio input, and the apparatus further comprises an inductor coupled between the first power stage output and a first speaker terminal, and a capacitor coupled between the first speaker terminal and a second speaker terminal, the second speaker terminal coupled to the second power stage output.
Conclusion
The prior arts made of record and not relied upon is considered pertinent to applicant's disclosure.
Cho et al. (20170149403), which is considered to be the closest prior art to the subject matter claimed, Cho et al. (Fig. 1B) discloses modulation circuit (200a) comprises first and second multiplexers (270a, 280a) and an output stage (400) having inputs (SCS) coupled to the outputs of the modulation circuit and outputs (VO+ and VO-). However, Cho et al. does not disclose first and second multiplexers (507 and 508) having respected inputs coupled to first and second outputs of the modulator.
Mahmoudidaryan et al. (20200266708) discloses first and second multiplexers. However, Mahmoudidaryan et al. does not disclose first and second multiplexers having respected inputs coupled to first and second outputs of the modulator.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Khanh V. Nguyen whose telephone number is (571) 272-1767. The examiner can normally be reached from 8:30 AM – 5:00 PM EST.
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/KHANH V NGUYEN/ Primary Examiner, Art Unit 2843
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