Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 4 and 10-17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by O’Mahony et al “A programmable Phase Rotator based on Time-Modulated Injection-Locking” (X-reference cited by the Applicant in Written Opinion of the ISA)(O’Mahony hereinafter).
Regarding claim 1, O’Mahony discloses a system (Fig. 2), comprising:
an oscillator (a 4-stage differential ring oscillator in Fig.2);
an injection circuit (inj[0], inj[1], inj[2], inj[3]) coupled to the oscillator, wherein the injection circuit comprises:
a first injection branch (left injection buffer for example as shown in inj[0]) coupled to a node (injection points between each stage), wherein the first injection branch is configured to receive a first clock signal (ckin{p,n}) and generate a first injection current based on the first clock signal;
a second injection branch (right injection buffer) coupled to the node, wherein the second injection branch is configured to receive a second clock signal (ckin{p,n}) and generate a second injection current based on the second clock signal, and wherein the first injection current and the second injection current are combined at the node, wherein the first clock signal and the second clock signal are phase offset from one another by 45 degrees (Fig 1 shows A, B, C, D 45° phases).
Regarding claim 4|1, O’Mahony discloses the system wherein:
the first injection branch is configured to set a strength of the first injection current based on a first control code (digital phase setting (ph_coarse)); and
the second injection branch is configured to set a strength of the second injection current based on a second control code (digital phase setting (ph_coarse)), wherein the first control code and the second control code are complementary (implied due to each differential stage output is 180°).
Regarding claim 10|1, O’Mahony discloses and implies the system wherein the first injection branch comprises:
a first input transistor (implied in the left buffer), wherein a gate of the first input transistor is configured to receive the first clock signal; and
a first strength control circuit (Phase decode logic) coupled between the node and a drain of the first input transistor, wherein the first strength control circuit is configured to control a strength of the first injection current based on a first control code (digital phase setting (ph_coarse)).
Regarding claim 11|10|1, O’Mahony discloses and implies the system wherein the second injection branch comprises:
a second input transistor (implied in the right buffer), wherein a gate of the second input transistor is configured to receive the second clock signal; and
a second strength control circuit (right Phase decode logic) coupled between the node and a drain of the second input transistor, wherein the second strength control circuit is configured to control a strength of the second injection current based on a second control code (digital phase setting (ph_coarse)).
Regarding claim 12|11|10|1, O’Mahony discloses the system wherein the first control code and the second control code are complementary (implied due to each differential stage output is 180°).
Regarding claim 13|11|10|1, O’Mahony discloses the system wherein the first strength control circuit comprises:
first transistors (implied in left side of Phase decode logic) coupled in parallel between the node and the drain of the first input transistor (implied due to ph_coarse[7:0]); and
a first controller (left Phase decode logic) configured to control a number of the first transistors that are turned on based on the first control code (ph_coarse[7:0]).
Regarding claim 14|13|11|10|1, O’Mahony discloses the system wherein the second injection branch comprises:
second transistors (implied in right side of Phase decode logic) coupled in parallel between the node and the drain of the second input transistor(implied due to ph_coarse[7:0]); and
a second controller(right Phase decode logic) configured to control a number of the second transistors that are turned on based on the second control code (ph_coarse[7:0]).
Regarding claim 15|14|13|11|10|1, O’Mahony discloses the system wherein the first control code and the second control code are complementary (implied due to each differential stage output is 180°).
Regarding claim 16|11|10|1, O’Mahony discloses the system wherein a source of the first input transistor is coupled to a ground, and a source of the second input transistor is coupled to the ground (implied due to use of NFETs).
Regarding claim 17|16|11|10|1, O’Mahony discloses and implies the system wherein the first input transistor comprises a first n-type field effect transistor (NFET) and the second input transistor comprises a second NFET.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over O’Mahony in view of McCune (US 8,508,309).
Regarding claim 5, O’Mahony discloses a system (Fig. 2), comprising:
an oscillator (a 4-stage differential ring oscillator);
an injection circuit (inj[0], inj[1], inj[2], inj[3]) coupled to the oscillator, wherein the injection circuit comprises:
a first injection branch (left injection buffer for example as shown in inj[0]) coupled to a node (injection points between each stage) wherein the first injection branch is configured to receive a first clock signal (ckin{p,n}) and generate a first injection current (left side path, implied in “injection buffer drive strength”) based on the first clock signal;
a second injection branch (left injection buffer for example as shown in inj[0]) coupled to the node, wherein the second injection branch is configured to receive a second clock signal (ckin{p,n}) and generate a second injection current based on the second clock signal, and wherein the first injection current (right side path) and the second injection current are combined at the node(injection points between each stage).
O’Mahony does not explicitly disclose a multiplexer configured to receive multiple clock signals, select the first clock signal and the second clock signal from among the multiple clock signals, output the first clock signal to the first injection branch, and output the second clock signal to the second injection branch.
McCune discloses a multiplexer (304 in FIG 5) configured to receive multiple clock signals (Θ1(t) … Θk(t)), select (by Θsel(t)) the first clock signal and the second clock signal from among the multiple clock signals, output the first clock signal to the first injection branch, and output the second clock signal to the second injection branch.
As known in the art, as an example shown in McCune, such a multiplexer is used to control multi-clocks to output the signals of interest by selection and therefore, it would have been obvious to one of ordinary skill in the art to modify the circuit of O’Mahony to include a multiplexer because such a modification would have been a mere substitution art recognized equivalent circuit of phase selection.
Regarding claim 6|5, O’Mahony discloses the system wherein the multiple clock signals are phase offset (ckin{p,n}) from one another.
Regarding claim 7|6|5, O’Mahony discloses the system wherein the multiple clock signals are phase offset from one another by 45 degrees (Fig 1 shows A, B, C, D 45° phases).
Regarding claim 8|5, McCune discloses the system, further comprising a multiphase generator (302 in FIG 5) configured to receive one or more input clock signals (308), generate the multiple clock signals based on the one or more input clock signals, and output the multiple clock signals (Θ1(t) … Θk(t)) to the multiplexer (304).
Regarding claim 9|8|5, the modification discloses the system wherein the one or more input clock signals comprise complementary clock signals (implied due to each differential stage output is 180°).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Joseph Chang whose telephone number is (571)272-1759. The examiner can normally be reached M-F 7:00- 17:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at 571-270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JOSEPH CHANG/ Primary Examiner, Art Unit 2849