Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-11 are present for examination.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al. (US20110273924A1) in view of Jin et al (US20080197712A1).
Regarding claim 1: Kang discloses a semiconductor memory device for voltage detecting (FIG. 2) comprising: a nonvolatile memory cell (FIG. 1); a detection circuit (330, FIG. 3) which detects a first voltage (VBLP) and selects one of a first mode (detection signal DET set HIGH, par. 44) and a second mode (detection signal DET set LOW, par. 44) based on the first voltage; wherein the detection circuit selects the first mode when the first voltage is equal to or greater than a determination value (detection signal DET set HIGH when VBLP is detected higher than reference voltage, par. 44), and selects the second mode when the first voltage is less than the determination value (detection signal DET set LOW when VBLP is detected lower than reference voltage, par. 44).
Kang does not disclose a transmitting unit which outputs a first signal corresponding to the one of the first mode and the second mode and the transmitting unit outputs the first signal of a first amplitude in the first mode, and outputs the first signal of a second amplitude that is smaller than the first amplitude in the second mode.
Jin does disclose a power device for power transmission (FIG. 1) comprising: a transmitting unit which outputs a first signal corresponding to the one of the first mode and the second mode (signal waveform corresponding to input voltage being compared to a threshold voltage, FIG. 3B), and the transmitting unit outputs the first signal of a first amplitude in the first mode (output signal waveform has higher amplitude when voltage level at load is above threshold voltage, FIG. 3B), and outputs the first signal of a second amplitude that is smaller than the first amplitude in the second mode (output signal waveform has lower amplitude when voltage level at load is below threshold voltage, FIG. 3B).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Kang with the transmission configuration of Jin to allow the system to output signals corresponding to the determined mode from the detected voltage, where the amplitudes of the signals are as defined like the claimed invention.
Regarding claim 6: Kang does not disclose a semiconductor memory device, wherein the first amplitude has an upper limit that is higher than an upper limit of the second amplitude.
Jin does disclose a power device for power transmission (FIG. 1) wherein the first amplitude has an upper limit that is higher than an upper limit of the second amplitude (output amplitude of first mode ‘high load’ has upper limit higher than upper limit of second mode ‘low load’, FIG. 3B).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Kang with the power transmission configuration of Jin to allow the system to have the defined relationship between the output amplitude of the different modes as the claimed invention.
Regarding claim 7: Kang does not disclose a semiconductor memory device, wherein the first amplitude has a lower limit that is equal to a lower limit of the second amplitude.
Jin does disclose a power device for power transmission (FIG. 1) wherein the first amplitude has a lower limit that is equal to a lower limit of the second amplitude (amplitude of first mode ‘high load’ has lower limit lower than lower limit of second mode ‘low load’, FIG. 3B).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Kang with the power transmission configuration of Jin to allow the system to have the defined relationship between the output amplitude of the different modes as the claimed invention.
Claim(s) 2 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al. (US20110273924A1) in view of Jin et al (US20080197712A1), in further view of Son et al. (US 20200135247 A1).
Regarding claim 2: Kang and Jin do not disclose a semiconductor device further comprising: a receiving unit which receives a second signal corresponding to the one of the first mode and the second mode; and a termination circuit coupled to the receiving unit.
Son does disclose a system of controlling on-die termination (ODT) comprising: a receiving unit (input-output pad PADS of a receiver device, par. 102, FIG. 14A and 15A) which receives a second signal (signal from transmission line TL, FIG. 14A and 15A) corresponding to the one of the first mode and the second mode; and a termination circuit (80-81, FIG. 14A and 15A) coupled to the receiving unit.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Kang and Jin with the configuration of Son to allow the device to have termination circuits in order to enhance signal integrity (par. 3).
Regarding claim 5: Kang and Jin do not disclose a semiconductor device, wherein the termination circuit is grounded with a first resistance value in the first mode and is grounded with a second resistance value that is larger than the first resistance value in the second mode.
Son does disclose a system of controlling on-die termination (ODT), wherein the termination circuit (81, FIG. 15A) is grounded (to ground voltage VSSQ, FIG. 15A) with a first resistance value (first resistance value M*Rtt, par. 118) in the first mode (read mode, par. 118) and is grounded with a second resistance value that is larger than the first resistance value (second resistance value M*Rtt+Rtg greater than first resistance value, par. 118) in the second mode (write mode, par. 118).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Kang and Jin with the configuration of Son to allow the system to have a similar relationship between this termination resistances based on modes like the claimed invention.
Claim(s) 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al. (US2011273924A1) in view of Jin et al (US2008197712A1), in further view of Son et al. (US 20200135247 A1), in further view of Ramachandra (US 20140185374 A1).
Regarding claim 3: Kang, Jin, and Son do not disclose a semiconductor, further comprising a reference voltage generator which generates one of a first reference voltage corresponding to the first mode and a second reference voltage corresponding to the second mode, wherein the receiving unit compares the second signal and the first reference voltage in the first mode, and compares the second signal and the second reference voltage in the second mode, to determine a logical level of the second signal.
Ramachandra does disclose a nonvolatile memory device (FIG. 1), further comprising a reference voltage generator (adaptive reference voltage level generator, FIG. 8) which generates one of a first reference voltage (Vref(POD), par. 68) corresponding to the first mode (corresponding to POD mode, par. 49) and a second reference voltage (Vref, par. 49) corresponding to the second mode (CTT mode, par. 48), wherein the receiving unit (receiver 420, FIG. 4) compares the second signal and the first reference voltage (compares output signal and a reference voltage Vref, FIG. 4) in the first mode, and compares the second signal and the second reference voltage in the second mode (compares output signal and a reference voltage Vref, FIG. 4), to determine a logical level of the second signal (Data, FIG. 4).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Kang, Jin, and Son with the configuration of Ramachandra to allow the system to share a similar setup of having a reference voltages used for comparisons between the outputted between the output signal and a determined reference voltage, chosen between the reference voltages based on the mode, like the claimed invention.
Regarding claim 4: Kang, Jin, and Son do not disclose a semiconductor, wherein the second reference voltage is lower than the first reference voltage.
Ramachandra does disclose a nonvolatile memory device (FIG. 1), wherein the second reference voltage (Vref(CTT), par. 57) is lower than the first reference voltage (Vref(POD) = Vref(CTT) + ΔV, par. 57).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Kang, Jin, and Son with the configuration of Ramachandra to allow the system to have the same relationship between reference voltages like the claimed invention.
Claim(s) 8 is rejected under 35 U.S.C. 103 as being unpatentable over Kang et al. (US2011273924A1) in view of Jin et al (US2008197712A1), in further view of Hanazawa et al. (US 20020175354 A1).
Regarding claim 8: Kang and Jin do not disclose a semiconductor device wherein: the transmitting unit includes an output drive including a first NMOS transistor and a second NMOS transistor which is coupled in series to the first NMOS transistor; and the first voltage is applied to a drain of the first NMOS transistor, a source of the first NMOS transistor is coupled to a drain of the second NMOS transistor, and the second voltage is applied to a source of the second NMOS transistor.
Hanazawa does disclose a semiconductor device wherein: the transmitting unit includes an output drive (driver, FIG. 1) including a first NMOS transistor (Mn3, FIG, 1) and a second NMOS transistor (Mn4, FIG. 1) which is coupled in series to the first NMOS transistor (FIG. 1); and the first voltage (voltage VR) is applied to a drain of the first NMOS transistor (FIG. 1), a source of the first NMOS transistor is coupled to a drain of the second NMOS transistor (FIG. 1), and the second voltage (voltage -VB) is applied to a source of the second NMOS transistor (FIG. 1).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Kang and Jin with the driver configuration of Hanazawa to allow the system to share the driver structure of the claimed invention.
Claim(s) 9 is rejected under 35 U.S.C. 103 as being unpatentable over Kang et al. (US2011273924A1) in view of Jin et al (US2008197712A1), in further view of Ramachandra (US 20140185374 A1).
Regarding claim 9: Kang and Jin do not disclose a semiconductor device, wherein the semiconductor memory device is a NAND flash memory.
Ramachandra does disclose a nonvolatile memory with detection and termination circuits wherein the semiconductor memory device is a NAND flash memory (flash memory arranged in NAND architecture, par. 15).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Kang and Jin with the configuration of Ramachandra to allow the system to be designed with NAND flash memory architecture like the claimed invention.
Claim(s) 10 are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al. (US2011273924A1) in view of Jin et al (US2008197712A1), in further view of Oh (US 20140082260 A1).
Regarding claim 10: Kang discloses a semiconductor memory device for voltage detecting (FIG. 2) comprising: a nonvolatile memory cell (FIG. 1); a detection circuit (330, FIG. 3) which detects a first voltage (VBLP) and selects one of a first mode (detection signal DET set HIGH, par. 44) and a second mode (detection signal DET set LOW, par. 44) based on the first voltage; wherein the detection circuit selects the first mode when the first voltage is equal to or greater than a determination value (detection signal DET set HIGH when VBLP is detected higher than reference voltage, par. 44), and selects the second mode when the first voltage is less than the determination value (detection signal DET set LOW when VBLP is detected lower than reference voltage, par. 44).
Kang does not disclose a transmitting unit which outputs a first signal corresponding to the one of the first mode and the second mode and the transmitting unit outputs the first signal of a first amplitude in the first mode, and outputs the first signal of a second amplitude that is smaller than the first amplitude in the second mode.
Jin does disclose a power device for power transmission (FIG. 1) comprising: a transmitting unit which outputs a first signal corresponding to the one of the first mode and the second mode (signal waveform corresponding to input voltage being compared to a threshold voltage, FIG. 3B), and the transmitting unit outputs the first signal of a first amplitude in the first mode (output signal waveform has higher amplitude when voltage level at load is above threshold voltage, FIG. 3B), and outputs the first signal of a second amplitude that is smaller than the first amplitude in the second mode (output signal waveform has lower amplitude when voltage level at load is below threshold voltage, FIG. 3B).
Kang and Jin do not disclose a memory controller which controls the semiconductor memory device and generates the first voltage.
Oh does disclose a flash memory controller (16, FIG. 1) which controls the semiconductor memory device (18, FIG. 1) and generates the first voltage (setting pads to an applied voltage to be detected, par. 7).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Kang and Jin with the configuration of Oh to have an external memory controller control the memory device.
Allowable Subject Matter
Claim(s) 11 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject
matter:
Claims include allowable subject matter since the prior art made of record and considered pertinent to the applicants’ disclosure, taken individually or in combination, does not teach or suggest the claimed invention having: the memory controller comprises: a second transmitting unit which outputs the second signal; a second receiving unit which receives the first signal; and a second termination circuit coupled to the second receiving unit as in claim 11.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHONY THINH TANG whose telephone number is (571)272-6845. The examiner can normally be reached Monday-Friday 7:30-5:00 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571)272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANTHONY THINH TANG/Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
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