DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “first thermal radiation structure vertically penetrates the core section and is exposed on the top and bottom surface of the core section” of claim 3 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 3 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 3, claim 3 recites “wherein the first thermal radiation structure vertically penetrates the core section and is exposed on the top and bottom surfaces of the core section”. However, claim 1, from which claim 3 depends, requires that “the first thermal radiation structure is electrically insulated from the upper and lower redistribution layer”. It is unclear how the first thermal radiation structure can be both electrically insulated from the upper and lower redistribution layer and the penetrate the core section and be exposed on the top and bottom surfaces of the core section. Further, the Applicant’s specification in Paragraph 0031 discusses the thermal radiation structure being exposed on the bottom surface but in this instance the embodiment discussed states that the lower dielectric pattern 122 electrically separates the thermal radiation structure from the lower wiring. However, the Applicant’s specification also states that the lower dielectric pattern 122 is part of the redistribution layer. Therefore, in embodiments discussed in the Applicant’s specification where the thermal radiation structures are exposed on the top and bottom of the core section, the thermal radiation structure is not electrically insulated from the upper and lower redistribution layers. Appropriate change is required to clarify the language.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4-7 and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Tong et al. (US 2024/0128150) hereinafter “Tong” in view of Yeh et al. (US 2022/0310532) hereinafter “Yeh”.
Regarding claim 1, Fig. 12 of Tong teaches a semiconductor package comprising: a wiring substrate (Item 105); an external connection terminal (Not labeled; solder balls on the bottom of Item 105) on a bottom surface of the wiring substrate (Item 105); a first semiconductor chip (Item 101) on the wiring substrate (Item 105); and a first chip stack (Item 102) on the wiring substrate (Item 105) and horizontally spaced from the first semiconductor chip (Item 101), wherein the wiring substrate (Item 105) includes: a core section (Combination of Items 1051 and 1052); an upper redistribution layer (Item 1101) that covers a top surface of the core section (Combination of Items 1051 and 1052); and a lower redistribution layer (Item 1102) that covers a bottom surface of the core section (Combination of Items 1051 and 1052), wherein the core section includes: a plurality of core through-vias (Items 1105) that vertically penetrate the core section; and a first thermal radiation structure (Item 107 and the liquid coolant that flows through it; Paragraph 0051) below the first chip stack (Item 102) and in the core section (Combination of Items 1051 and 1052), wherein the first thermal radiation structure (Item 107) is electrically insulated from the upper and lower redistribution layers (Items 1101 and 1102, respectively), and wherein a thermal conductivity of the first thermal radiation structure (Paragraph 0051 where liquid coolant flow through Items 107) is greater than a thermal conductivity of the core section (Combination of Items 1051 and 1052).
Tong does not teach an interposer substrate on a top surface of the wiring substrate nor where the first semiconductor chip and the first chip stack are on the interposer substrate.
Fig. 13A of Yeh teaches where a first chip stack (Item 230; Paragraph 0064) and a first semiconductor chip (Item 240) are on an interposer substrate (Paragraph 0129 where an interposer is present although not shown in the drawings) such that an interposer substrate is on a top surface of a wiring substrate (Item 300A) between the wiring substrate and a group (Item P1) of first chip stack (Item 230) and first semiconductor chip (Item 240).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have an interposer substrate on a top surface of the wiring substrate and where the first semiconductor chip and the first chip stack are on the interposer substrate because the interposer may provide further routing function to the first semiconductor chip and the first chip stack (Yeh Paragraph 0129).
Regarding claim 4, Fig. 12 of tong further teaches where the first thermal radiation structure (Item 107) is spaced apart from the top and bottom surfaces of the core section (Combination of Items 1051 and 1052), and the core section (Combination of Items 1051 and 1052) separates the upper and lower redistribution layers (Items 1102 and 1101, respectively) from the first thermal radiation structure (Item 107).
Under an alternate interpretation of Tong, Regarding claim 1, Fig. 12 of Tong teaches a semiconductor package comprising: a wiring substrate (Item 105); an external connection terminal (Not labeled; solder balls on the bottom of Item 105) on a bottom surface of the wiring substrate (Item 105); a first semiconductor chip (Item 101) on the wiring substrate (Item 105); and a first chip stack (Item 102) on the wiring substrate (Item 105) and horizontally spaced from the first semiconductor chip (Item 101), wherein the wiring substrate (Item 105) includes: a core section (Combination of Items 1051 and 1052); an upper redistribution layer (Item 1101) that covers a top surface of the core section (Combination of Items 1051 and 1052); and a lower redistribution layer (Item 1102) that covers a bottom surface of the core section (Combination of Items 1051 and 1052), wherein the core section includes: a plurality of core through-vias (Items 1105) that vertically penetrate the core section; and a first thermal radiation structure (Left Item 107 and the liquid coolant that flows through it; Paragraph 0051) below the first chip stack (Item 102) and in the core section (Combination of Items 1051 and 1052), wherein the first thermal radiation structure (Left Item 107) is electrically insulated from the upper and lower redistribution layers (Items 1101 and 1102, respectively), and wherein a thermal conductivity of the first thermal radiation structure (Paragraph 0051 where liquid coolant flow through Item 107) is greater than a thermal conductivity of the core section (Combination of Items 1051 and 1052).
Tong does not teach an interposer substrate on a top surface of the wiring substrate nor where the first semiconductor chip and the first chip stack are on the interposer substrate.
Fig. 13A of Yeh teaches where a first chip stack (Item 230; Paragraph 0064) and a first semiconductor chip (Item 240) are on an interposer substrate (Paragraph 0129 where an interposer is present although not shown in the drawings) such that an interposer substrate is on a top surface of a wiring substrate (Item 300A) between the wiring substrate and a group (Item P1) of first chip stack (Item 230) and first semiconductor chip (Item 240).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have an interposer substrate on a top surface of the wiring substrate and where the first semiconductor chip and the first chip stack are on the interposer substrate because the interposer may provide further routing function to the first semiconductor chip and the first chip stack (Yeh Paragraph 0129).
Under the alternate interpretation of Tong, Regarding claim 2, Fig. 12 of Tong further teaches where, when viewed in the plan, the first thermal radiation (Left Item 107) structure is horizontally spaced apart from the first semiconductor chip (Item 101).
Under the alternate interpretation of Tong, Regarding claim 5, Figs. 3 and 12 of Tong further teaches a second chip stack (Item 102) on the interposer substrate (when combined with Yeh as stated in the rejection of claim 1 above) and spaced apart in a first direction from the first chip stack; and a second thermal radiation structure (Another of Items 107) below the second chip stack (Item 102) and in the core section (Combination of Items 1052 and 1051), wherein the first thermal radiation structure (Left Item 107) and vertically overlaps the first chip stack (Item 102), and wherein the second thermal radiation structure (Another of Items 107) vertically overlaps the second chip stack (Item 102).
Under the alternate interpretation of Tong, Regarding claim 6, Figs. 3 and 12 of Tong further teaches where the first semiconductor chip (Item 101) is spaced apart in a second direction from the first chip stack (Item 102), the second direction intersecting the first direction, the first thermal radiation structure (Left Item 107) and the second thermal radiation structure (Another Item 107) are connected into a single thermal radiation structure, and the single thermal radiation structure vertically overlaps all of the first and second chip stacks (Items 102).
Under the alternate interpretation of Tong, Regarding claim 7, Figs. 3 and 12 of Tong further teaches the first semiconductor chip (Item 101) is between the first chip stack (Item 102) and the second chip stack (Item 102), the first thermal radiation structure (Left Item 107) and the second thermal radiation structure (Another Item 107) are connected into one thermal radiation structure, and when viewed in plan, the one thermal radiation structure surrounds the first semiconductor chip (Item 101).
Regarding claim 16, Fig. 12 of Tong teaches a semiconductor package comprising:a core section (Combination of Items 1051 and 1052); a thermal radiation structure (Item 107 and the liquid coolant inside of it) in the core section (Combination of Items 1051 and 1052); a first redistribution layer (Item 1101) and a second redistribution layer (Item 1102) respectively on a top surface and a bottom surface of the core section (Combination of Items 1051 and 1052), each of the first and second redistribution layers (Items 1101 and 1102, respectively) including a dielectric pattern and a wiring pattern in the dielectric pattern (Paragraph 0068); a first semiconductor chip (Item 101) on a wiring substrate (Item 105); a plurality of chip stacks (Item 102) on the wiring substrate (Item 105) and horizontally spaced apart from the first semiconductor chip (Item 101), each of the plurality of chip stacks (Item 102) including a plurality of semiconductor chips that are vertically stacked, wherein the thermal radiation structure (Item 107 and the liquid coolant within it) vertically overlaps the plurality of chip stacks.
Tong does not teach an interposer substrate on the first redistribution layer nor a first semiconductor chip and a plurality of chip stacks on the interposer substrate.
Fig. 13A of Yeh teaches where a first chip stack (Item 230; Paragraph 0064) and a first semiconductor chip (Item 240) are on an interposer substrate (Paragraph 0129 where an interposer is present although not shown in the drawings) such that an interposer substrate is on a top surface of a wiring substrate (Item 300A) between the wiring substrate and a group (Item P1) of first chip stack (Item 230) and first semiconductor chip (Item 240).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have an interposer substrate on the first redistribution layer and where the first semiconductor chip and the plurality of chip stacks are on the interposer substrate because the interposer may provide further routing function to the first semiconductor chip and the first chip stack (Yeh Paragraph 0129).
Regarding claim 17, Fig. 12 of Tong further teaches where, when viewed in plan, the thermal radiation structure (Item 107 and the liquid coolant within it) is horizontally spaced apart from the first semiconductor chip (Item 101).
Regarding claim 18, Fig. 12 of Tong further teaches where the thermal radiation structure (Item 107 and the liquid coolant within) forms a through hole (Area between respective fluidic channels of Item 107 that are under Item 101) that penetrates the thermal radiation structure (Item 107), the core section (Combination of Items 1051 and 1052) fills the through hole, and the through hole is below the first semiconductor chip (Item 101).
Regarding claim 19, Fig. 12 of Tong further teaches where the core section (Combination of Items 1051 and 1052) extends between the thermal radiation structure (Item 107 and the liquid coolant within it) and the first redistribution layer (Item 1101) and between the thermal radiation structure (Item 107 and the liquid coolant within it) and the second redistribution layer (Item 1102).
Regarding claim 20, Fig. 12 of Tong further teaches at least one through-via (Item 1105) that penetrates the core section (Combination of Items 1051 and 1052) and connects the first redistribution layer (Item 1101) and the second redistribution layer (Item 1102).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Tong et al. (US 2024/0128150) hereinafter “Tong” in view of Yeh et al. (US 2022/0310532) hereinafter “Yeh” and in further view of Feng et al. (US 2025/0038063) hereinafter “Feng”.
Regarding claim 8, the combination of Tong and Yeh teaches all of the elements of the claimed invention as stated above except where the first thermal radiation structure includes at least one metal post in the core section.
Tong does not teach where the first thermal radiation structure includes at least one metal post in the core section.
Fig. 1 of Feng teaches where a thermal radiation structure (Item 148) is present in a core section (Item 120) where the thermal radiation structure (Item 148) includes at least one metal post (Paragraph 0049; where the post is oriented horizontally).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the thermal radiation structure include at least one metal post in the core section because at least one metal post is known to be configured to transmit heat from the device (Feng Paragraph 0048).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Tong et al. (US 2024/0128150) hereinafter “Tong” in view of Yeh et al. (US 2022/0310532) hereinafter “Yeh” and in further view of Feng et al. (US 2025/0038063) hereinafter “Feng” and Leitgeb et al. (US 2023/0300982) hereinafter “Leitgeb”.
Regarding claim 9, the combination of Tong, Yeh and Feng teaches all of the elements of the claimed invention as stated above.
Tong does not teach where the first thermal radiation structure includes a plurality of metal posts in the core section.
Tong further teaches where the first thermal radiation structure comprises a plurality of channels (Item 107).
Feng teaches where a thermal radiation structure (Item 148) is a metal post.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the first thermal metal post, as stated in Feng, under each of the chips in Tong such that the first thermal radiation structure includes a plurality of metal posts in the core section because this configuration is known to transmit heat from the device (Feng Paragraph 0048).
Tong does not teach where a width of each metal post of the plurality of metal posts is greater than a width of each core through-via of the core through-vias.
However, Lin teaches where a width of a thermal radiation metal is a result effective variable (Paragraph 0027 where the width and thickness of metal lines may be increased to increase heat dissipation efficiency). In In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977), the CCPA held that a particular parameter must first be recognized as a result-effective variable, i.e., a variable which achieves a recognized result, before the determination of the optimum or workable ranges of said variable might be characterized as routine experimentation, because "obvious to try" is not a valid rationale for an obviousness finding (MPEP 2144.05).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to optimize the width of each metal post such that a width of each metal post of the plurality of metal posts is greater than a width of each core through-via of the core through-vias because "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (MPEP 2144.05).
Claims 10-14 are rejected under 35 U.S.C. 103 as being unpatentable over Tong et al. (US 2024/0128150) hereinafter “Tong” in view of Feng et al. (US 2025/0038063) hereinafter “Feng”.
Regarding claim 10, Fig. 12 of Tong teaches a semiconductor package comprising: a first redistribution layer (Item 1101); a core section (Combination of Items 1051 and 1052) on the first redistribution layer (Item 1102), the core section (Combination of Items 1051 and 1052) having a central region (Portion under Item 101) and a peripheral region (Remaining portion) that surrounds the central region; a thermal radiation structure (Item 107 and liquid coolant inside of it) in the core section (Combination of Items 1051 and 1052) on the peripheral region; a second redistribution layer (Item 1101) on the core section (Combination of Items 1051 and 1052); a first chip stack (Item 102) on the second redistribution layer (Item 1101) on the peripheral region, the first chip stack (Item 102) including a plurality of memory chips (Paragraph 0052) vertically stacked; and a logic chip (Item 101) on the second redistribution layer (Item 1101) on the central region (Portion under Item 101) and horizontally spaced apart from the first chip stack (Item 102), where the thermal radiation structure (Item 107 and liquid coolant inside of it) is spaced apart from top and bottom surfaces of the core section (Combination of Items 1051 and 1052).
Tong does not teach where the thermal radiation structure is a thermal radiation metal.
Fig. 1 of Feng teaches where a thermal radiation structure (Item 148) is present in a core section (Item 120) where the thermal radiation structure (Item 148) is a thermal radiation metal (Paragraph 0049) and is spaced apart from a top and bottom of the core section.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the thermal radiation structure be a thermal radiation metal because a thermal radiation metal is known to be configured to transmit heat from the device (Feng Paragraph 0048).
Regarding claim 11, Fig. 3 of Tong further teaches a second chip stack (Item 102) on the second redistribution layer (Item 1101) on the peripheral region, wherein the first chip stack and the second chip stack (Items 102) are spaced apart from each other in a first direction, and wherein the logic chip (Item 101) is spaced apart in a second direction from the first chip stack (Item 102), the second direction intersecting the first direction.
Regarding claim 12, Fig. 12 of Tong further teaches where, when viewed in plan, the thermal radiation structure (Item 107; thermal radiation metal when combined with Feng as stated above) extends from a location below the first chip stack to a location below the second chip stack (Where the cavities are connected to each other).
Regarding claim 13, Fig. 12 of Tong further teaches where the core section (Combination of Items 1051 and 1052) is formed of a dielectric material.
Regarding claim 14, Fig. 12 of Tong further teaches where the core section (Combination of Items 1051 and 1052) includes a through via (Item 1105) that vertically penetrates the core section and that electrically connects the first redistribution layer (Item 1102) and the second redistribution layer (Item 1101) to each other wherein the thermal radiation structure (Item 107) is in the peripheral region.
Tong does not teach where the thermal radiation structure is a thermal radiation metal including a metal post.
Fig. 1 of Feng teaches where a thermal radiation structure (Item 148) is present in a core section (Item 120) where the thermal radiation structure (Item 148) is a thermal radiation metal (Paragraph 0049) that includes a post.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the thermal radiation structure be a thermal radiation metal including a metal post because a thermal radiation metal post is known to be configured to transmit heat from the device (Feng Paragraph 0048).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Tong et al. (US 2024/0128150) hereinafter “Tong” in view of Feng et al. (US 2025/0038063) hereinafter “Feng” and in further view of Lin et al. (US 2014/0084445) hereinafter “Lin” and Leitgeb et al. (US 2023/0300982) hereinafter “Leitgeb”.
Regarding claim 15, the combination of Tong and Feng teaches all of the elements of the claimed invention as stated above.
Tong does not teach where a first width of at least one metal post is greater than a second width of the through-via.
However, Lin teaches where a width of a thermal radiation metal is a result effective variable (Paragraph 0027 where the width and thickness of metal lines may be increased to increase heat dissipation efficiency). In In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977), the CCPA held that a particular parameter must first be recognized as a result-effective variable, i.e., a variable which achieves a recognized result, before the determination of the optimum or workable ranges of said variable might be characterized as routine experimentation, because "obvious to try" is not a valid rationale for an obviousness finding (MPEP 2144.05).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to optimize the first width of the at least one metal post such that a first width of the at least one metal post is greater than a second width of the through via because "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (MPEP 2144.05).
Tong does not teach where the at least one metal post is electrically insulated from the first and second redistribution layer.
Leitgeb teaches where a metal block may be embedded with an insulating material coating such to facilitate heat dissipation (Paragraph 0047).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the at least one metal post be electrically insulated from the first and second redistribution layer because embedded metal being electrically insulated from other electrical structures is known to facilitate heat dissipation (Leitgeb Paragraph 0047).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC K ASHBAHIAN whose telephone number is (571)270-5187. The examiner can normally be reached 8-5:30 PM.
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/ERIC K ASHBAHIAN/Primary Examiner, Art Unit 2891
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