Prosecution Insights
Last updated: October 25, 2026
Application No. 18/732,697

PACKAGED SEMICONDUCTOR DEVICES AND METHODS OF MAKING THE SAME

Non-Final OA §103§112
Filed
Jun 04, 2024
Priority
Jun 07, 2023 — CN 202310670954.2
Examiner
CHOU, SHIH TSUN A
Art Unit
2811
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
NXP Semiconductors N.V.
OA Round
1 (Non-Final)
78%
Grant Probability
Favorable
1-2
OA Rounds
1m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allowance Rate
380 granted / 489 resolved
+9.7% vs TC avg
Strong +16% interview lift
Without
With
+15.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
22 currently pending
Career history
521
Total Applications
across all art units

Statute-Specific Performance

§103
51.4%
+11.4% vs TC avg
§102
21.7%
-18.3% vs TC avg
§112
26.5%
-13.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 489 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Invention II, claims 10-19, in the reply filed on 8/19/2026 is acknowledged. Claims 1-9 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 8/19/2026. Claim Objections Claim 11 is objected to because of the following informalities: a comma is suggested to be added after the preamble “The method of claim 10”. Claim 12 is objected to because of the following informalities: a comma is suggested to be added after the preamble “The method of claim 10”. Claim 16 is objected to because of the following informalities: the text “the step” is suggested to be changed to “a step’ for clarity. Claim 17 is objected to because of the following informalities: the text “the step” is suggested to be changed to “a step’ for clarity. Claim 19 is objected to because of the following informalities: the text “a” before “locating the semiconductor die” is suggested to be deleted for clarity. Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 12 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 12 recites the limitation "the stud" in line 1. There is insufficient antecedent basis for this limitation in the claim. The following is a quotation of 35 U.S.C. 112(d): (d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers. The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph: Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers. Claim 14 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. More particularly, Claim 14 fails to further limit the subject matter of claim 13. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 10-12 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Fjelstad (US 6,001,671) in view of Kageyama (US 2022/0139815). Regarding claim 10, Fjelstad discloses, in FIGS. 1A-1F and 1G-1 and in related text, a method of manufacturing a packaged semiconductor die, the method comprising: providing a metal foil (100) (see Fjelstad, FIG. 1A, column 3, lines 53-67); affixing a semiconductor die (120) on the metal foil by a (thermally) conductive epoxy (135); bonding a plurality of studs (111) onto the metal foil around the semiconductor die (see Fjelstad, FIGS. 1B-1C, column 4, lines 1-45); wire bonding the semiconductor die to the plurality of studs (see Fjelstad, FIG. 1D-1, column 4, lines 46-55); encapsulating the semiconductor die, wire bonds, and studs with an encapsulant (see Fjelstad, FIG. 1E, column 4, lines 56-65); removing the metal foil (see Fjelstad, FIG. 1F, column 4, line 66 to column 5, line 10); and singulating the packaged semiconductor die (see Fjelstad, FIG. 1G-1, column 5, lines 11-26). Fjelstad does not explicitly discloses providing a metal foil on a carrier substrate; removing the carrier substrate. Kageyama teaches providing a metal foil (811) on a carrier substrate (800) (see Kageyama, FIG. 4, [0050]-[0051]); removing the carrier substrate (see Kageyama, FIG. 13, [0064]). Fjelstad and Kageyama are analogous art because they both are directed to semiconductor packaging and one of ordinary skill in the art would have had a reasonable expectation of success to modify Fjelstad with the features of Kageyama because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Fjelstad to include providing a metal foil on a carrier substrate; removing the carrier substrate, as taught by Kageyama, to provide a support substrate in the preparatory process of a manufacturing method (see Kageyama, [0048]-[0050]). Regarding claim 11, Fjelstad in view of Kageyama teaches the method of claim 10. Fjelstad discloses wherein the metal foil (100) is a one of aluminium and copper (see Fjelstad, column 3, lines 53-67). Regarding claim 12, Fjelstad in view of Kageyama teaches the method of claim 10. Fjelstad discloses wherein the stud (111) is copper (see Fjelstad, column 4, lines 1-31). Regarding claim 18, Fjelstad in view of Kageyama teaches the method of claim 10. Kageyama teaches wherein the metal foil (811) is affixed to the carrier substrate (800) by an adhesive (810) (see Kageyama, FIG. 4, [0050]-[0051]), with the same analogous prior art and field of endeavor statement and the same motivation as provided for in claim 10. Claims 10, 13-14, 16-17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Embong (US 2009/0042339) in view of Heng (US 2015/0084213). Regarding claim 10, Embong discloses, in FIGS. 3A-3E and in related text, a method of manufacturing a packaged semiconductor die, the method comprising: providing a metal foil (302); affixing a semiconductor die (310) on the metal foil by a (thermally) conductive epoxy (308) (see Embong, FIGS. 3B-3C, [0015], [0017]-[0018]); bonding a plurality of studs (314) onto the metal foil around the semiconductor die; wire bonding the semiconductor die to the plurality of studs (see Embong, FIGS. 3A and 3C, [00190]-[0020]); encapsulating the semiconductor die, wire bonds, and studs with an encapsulant (315) (see Embong, FIG. 3D, [0020]); removing the metal foil (see Embong, FIG. 3E, [0021]); and singulating the packaged semiconductor die (see Embong, [0029]). Embong does not explicitly disclose providing a metal foil on a carrier substrate; removing the carrier substrate. Heng teaches providing a metal foil (142) on a carrier substrate (140) (see Heng, FIG. 4a, [0045]); removing the carrier substrate (see Heng, FIG. 4e, [0048]). Embong and Heng are analogous art because they both are directed to semiconductor packaging and one of ordinary skill in the art would have had a reasonable expectation of success to modify Embong with the features of Heng because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Embong to include providing a metal foil on a carrier substrate; removing the carrier substrate, as taught by Heng, to provide a sacrificial base and rigid material for structural support (see Heng, [0045]). Regarding claim 13, Embong in view of Heng teaches the method of claim 10. Embong discloses wherein the studs have a diameter in a range of 100 µm to 200 µm (see Embong, FIG. 4E, [0025]: diameter of bonding wire 414 is 1 mil or 25.4 µm, or 5 mil or 127 µm, and is less than diameter of diameter of stud 417, that is, diameter of stud is greater than at least 25.4 µm). Regarding claim 14, Embong in view of Heng teaches the method of claim 13. Embong discloses wherein the studs have a diameter in a range of 100 µm to 200 µm (see discussion on claim 13 above). Regarding claim 17, Embong in view of Heng teaches the method of claim 13. Embong discloses prior to singulating the packaged semiconductor die, the step of attaching solder balls to the studs (see Embong, [0017], [0019], [0029]). Regarding claim 16, Embong in view of Heng teaches the method of claim 10. Embong discloses prior to singulating the packaged semiconductor die, the step of attaching solder balls to the studs (see Embong, [0017], [0019], [0029]). Regarding claim 19, Embong in view of Heng teaches the method of claim 10. Embong discloses wherein the metal foil (302) comprises at least one fiducial mark (306) for a locating the semiconductor die (see Embong, FIG. 3A, [0019]: fiducial marks 306 define locations of studs 314, which surround semiconductor die 310). Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Embong in view of Heng, and further in view of Warren (US 2013/0087915). Regarding claim 15, Embong in view of Heng teaches the method of claim 10. Embong discloses the step of bonding a plurality of studs onto the metal foil around the semiconductor die (see discussion on claim 10 above). Embong does not explicitly disclose wherein the step of bonding a plurality of studs onto the metal foil comprises thermosonic bonding. Warren teaches wherein the step of bonding a plurality of studs onto the metal foil comprises thermosonic bonding (see Warren, FIG. 1B, [0025]). Embong and Warren are analogous art because they both are directed to semiconductor packaging and one of ordinary skill in the art would have had a reasonable expectation of success to modify Embong with the features of Warren because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Embong to include wherein the step of bonding a plurality of studs onto the metal foil comprises thermosonic bonding, as taught by Warren, to directly bond stud bump to a single metal finish (see Warren, [0025]). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHIH TSUN A CHOU whose telephone number is (408)918-7583. The examiner can normally be reached M-F 8:00-16:00 Arizona Time. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at (571) 272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SHIH TSUN A CHOU/Primary Examiner, Art Unit 2811
Read full office action

Prosecution Timeline

Jun 04, 2024
Application Filed
Oct 15, 2026
Non-Final Rejection mailed — §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12772901
Laser Lift-Off Processing System Including Metal Grid
4y 2m to grant Granted Oct 20, 2026
Patent 12772823
BACKSIDE CONTACT WITH FULL WRAP-AROUND CONTACT
4y 1m to grant Granted Oct 20, 2026
Patent 12772747
TEMPLATING LAYERS FOR GROWTH OF PERPENDICULARLY MAGNETIZED HEUSLER FILMS
3y 3m to grant Granted Oct 20, 2026
Patent 12772525
Composite Structure, Method for Manufacturing the same and Non-Volatile Optical Memory Device
2y 10m to grant Granted Oct 20, 2026
Patent 12765265
PERPENDICULAR SHAPE ANISOTROPY DESIGN WITH ASYMMETRIC COMPOSITE FREE LAYER
3y 7m to grant Granted Oct 13, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
78%
Grant Probability
94%
With Interview (+15.9%)
2y 5m (~1m remaining)
Median Time to Grant
Low
PTA Risk
Based on 489 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month