DETAILED ACTION
The present application, filed 06/04/2024, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Objections
Claim 13 is objected to because of the following informalities: it appears that “a bias signal” (line 4) should be “the bias signal”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ho (US 10,281,943) in view of Chaung et al. (“Chuang”, US 2024/0162867).
Re claim 17, Ho teaches an operation method of a voltage regulator [Fig 2], the method comprising: generating a first voltage [at N1] by comparing a reference voltage [VREF] and a feedback voltage [FB] of an output voltage [at OUT]; generating a second voltage [at N2], based on the first voltage and a bias signal [FBX]; and generating the output voltage [via MN], based on the second voltage, but does not teach the bias signal including a high-frequency component of a power supply voltage of the voltage regulator.
Chuang teaches a device [Fig 2B] that generates a bias signal [VCM2] including a high-frequency component [SN1] of a power supply voltage [VDD] of the voltage regulator [paragraph 25]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Ho to include the features of Chuang because it is used reduce system instability while enhancing system performance, thus improving the utility of the device, which increases efficiency.
Re claim 18, Ho teaches wherein the first voltage is generated by amplifying a difference between the output voltage [at VOUT] and the feedback voltage [at FB].
Re claim 19, Ho teaches the limitations as applied to the claim above but does not teach wherein the bias signal is generated by a power noise replica buffer unit, wherein the power noise replica buffer unit includes: a high-pass filter configured to extract the high-frequency component of the power supply voltage of the voltage regulator; and an amplifier configured to generate the bias signal by amplifying the high-frequency component.
Chuang teaches a device [Fig 2B] wherein the bias signal is generated by a power noise replica buffer unit, wherein the power noise replica buffer unit includes: a high-pass filter [241] configured to extract the high-frequency component [e,g., noise] of the power supply voltage of the voltage regulator [paragraph 25]; and an amplifier [243] configured to generate the bias signal by amplifying the high-frequency component. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Ho to include the features of Chuang because it is used reduce system instability while enhancing system performance, thus improving the utility of the device, which increases efficiency.
Re claim 20, Ho teaches wherein the output voltage is generated by a transistor [MN] including a first end connected to a power node [at VIN] and configured to operate in response to the second voltage [at N2].
Allowable Subject Matter
Claims 1-16 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: the prior art fails to teach or disclose:
Re claim 1 and its dependents thereof, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “the power noise replica buffer unit includes: a 0-th transistor connected between a ground node and a 0-th node, and configured to operate in response to the second voltage; a first transistor connected between the 0-th node and a power node and including a gate node connected to a second node; a high-pass filter connected between the second node and a third node; a second transistor connected between the power node and a first node connected to the third node and including a gate node connected to the third node; and a current source connected between the first node and the ground node” in combination with the additionally claimed features, as are claimed by Applicant.
Re claim 9 and its dependents thereof, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “a first buffer configured to generate a third voltage, based on the bias signal and the second voltage; a second buffer configured to buffer a fourth voltage, based on the third voltage” in combination with the additionally claimed features, as are claimed by Applicant.
Conclusion
Examiner's Note:
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAKAISHA JACKSON whose telephone number is (571)270-3111. The examiner can normally be reached on M-F 8:00-5:00.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MONICA LEWIS can be reached on 571-272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LaKaisha Jackson/
Examiner, Art Unit 2838