DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 11-12 and 16 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Wang (US Publication No. 20150236500).
Regarding claim 1, Wang discloses a device (i.e., such as device 100; see for example fig. 1, para. [0021]- [0032]) comprising: a first silicon-controlled rectifier (i.e., such as SCR 102; see for example fig. 1, para. [0021]- [0032]) comprising a first PNP bipolar junction transistor (BJT) (i.e., such as BJT/PNP/114; see for example fig. 1, para. [0021]- [0032]) and a first NPN BJT (i.e., such as BJT/NPN/116; see for example fig. 1, para. [0021]- [0032]) in which bases (i.e., such as B/114-2 = C/116-1 = 134 = N-well; see for example fig. 1, para. [0021]- [0032]) and collectors (i.e., such as C/114-3 = B/116-2 = 136 = P-well; see for example fig. 1, para. [0021]- [0032]) are cross-coupled (i.e., such as B/114-2 and C/116-1 are cross-coupled in 134/P-well; similarly, C/114-3 and B/116-2 are cross-coupled in 136/P-well; see for example fig. 1, para. [0021]- [0032]); and a field effect transistor (FET) (i.e., such as FET 124; see for example fig. 1, para. [0021]- [0032]) configured (i.e., such as FET 124 is configured to discharge any ESD event; see for example fig. 1, para. [0021]- [0032]) to, based on an electrostatic discharge (i.e., such as any ESD event; see for example fig. 1, para. [0021]- [0032]) occurring between an anode (i.e., such as anode terminal 110/PAD; see for example fig. 1, para. [0021]- [0032]) of the first silicon-controlled rectifier (i.e., such as SCR 102; see for example fig. 1, para. [0021]- [0032]) and a cathode (i.e., such as cathode terminal 112/GND; see for example fig. 1, para. [0021]- [0032]) of the first silicon-controlled rectifier (i.e., such as SCR 102; see for example fig. 1, para. [0021]- [0032]), trigger (i.e., such as trigger; for instance, when the voltage applied to the SCR becomes higher than the trigger voltage V.sub.tr of the SCR, avalanche breakdown occurs at the N-P junction formed by the N-well and the P-well; see for example fig. 1, para. [0021]- [0032]) the first silicon-controlled rectifier (i.e., such as SCR 102; see for example fig. 1, para. [0021]- [0032]), wherein an emitter (i.e., such as E = 114-1 = 140 = p+; see for example fig. 1, para. [0021]- [0032]) of the first PNP BJT (i.e., such as BJT/PNP/114; see for example fig. 1, para. [0021]- [0032]) corresponds to a plurality of first p+ regions (i.e., such as plurality of p+ regions 142, 140, 150, 160, etc.; see for example fig. 1, para. [0021]- [0032]) being spaced apart (i.e., such as p+/142 and p+/140 are spaced apart via n+/144 and n+/161; see for example fig. 1, para. [0021]- [0032]) from each other (i.e., such as p+/142, n+/144, n+/161, p+/140, n+/138, etc.; see for example fig. 1, para. [0021]- [0032]) in a first direction (i.e., such as X-axis/left-right direction; see for example fig. 1, para. [0021]- [0032]), and wherein the FET (i.e., such as FET 124; see for example fig. 1, para. [0021]- [0032]) is connected (i.e., such as drain D/124-1 of FET 124 is connected to the SCR 102 trigger terminal R-118/B-114-2/C-116-1 via emitter E/122-1 of transistor 122 and gate G/124-2 is connected to the SCR 102 cathode/112/GND terminal via resistor 128 and source S/124-3 is connected to the SCR 102 cathode/112/GND terminal via collector C/122-3 of transistor 122; see for example fig. 1, para. [0021]- [0032]) to the first silicon-controlled rectifier (i.e., such as SCR 102; see for example fig. 1, para. [0021]- [0032]) through at least one first n+ region (i.e., such as n+ regions 144, 161, 138, 152, 154, 156, etc.; see for example fig. 1, para. [0021]- [0032]) disposed between (i.e., such as n+/144 is between p+/142 on the left-side at P-well 136 and p+/140 on the right-side at N-well 134; see for example fig. 1, para. [0021]- [0032]) the plurality of first p+ regions (i.e., such as plurality of p+ regions 142, 140, 150, 160, etc.; see for example fig. 1, para. [0021]- [0032]).
Regarding claim 11, Wang discloses a device (i.e., such as device 100; see for example fig. 1, para. [0021]- [0032]); wherein the FET (i.e., such as FET 124; see for example fig. 1, para. [0021]- [0032]) is an n-channel field effect transistor (NFET) (i.e., such as NFET 124; see for example fig. 1, para. [0021]- [0032]), wherein the NFET (i.e., such as NFET 124; see for example fig. 1, para. [0021]- [0032]) comprises: a gate (i.e., such as gate G/124-2; see for example fig. 1, para. [0021]- [0032]) electrically connected (i.e., such as drain D/124-1 of FET 124 is connected to the SCR 102 trigger terminal R-118/B-114-2/C-116-1 via emitter E/122-1 of transistor 122 and gate G/124-2 is connected to the SCR 102 cathode/112/GND terminal via resistor 128 and source S/124-3 is connected to the SCR 102 cathode/112/GND terminal via collector C/122-3 of transistor 122; see for example fig. 1, para. [0021]- [0032]) to the cathode (i.e., such as cathode terminal 112/GND; see for example fig. 1, para. [0021]- [0032]); a source (i.e., such as source S/124-3; see for example fig. 1, para. [0021]- [0032]) electrically connected (i.e., such as drain D/124-1 of FET 124 is connected to the SCR 102 trigger terminal R-118/B-114-2/C-116-1 via emitter E/122-1 of transistor 122 and gate G/124-2 is connected to the SCR 102 cathode/112/GND terminal via resistor 128 and source S/124-3 is connected to the SCR 102 cathode/112/GND terminal via collector C/122-3 of transistor 122; see for example fig. 1, para. [0021]- [0032]) to the cathode (i.e., such as cathode terminal 112/GND; see for example fig. 1, para. [0021]- [0032]); and a drain (i.e., such as drain D/124-1; see for example fig. 1, para. [0021]- [0032]) electrically connected (i.e., such as drain D/124-1 of FET 124 is connected to the SCR 102 trigger terminal R-118/B-114-2/C-116-1 via emitter E/122-1 of transistor 122 and gate G/124-2 is connected to the SCR 102 cathode/112/GND terminal via resistor 128 and source S/124-3 is connected to the SCR 102 cathode/112/GND terminal via collector C/122-3 of transistor 122; see for example fig. 1, para. [0021]- [0032]) to the at least one first n+ region (i.e., such as n+ regions 154, 156; see for example fig. 1, para. [0021]- [0032]).
Regarding claim 12, Wang discloses a device (i.e., such as device 100; see for example fig. 1, para. [0021]- [0032]); further comprising: a capacitor (i.e., such as capacitor 126; see for example fig. 1, para. [0021]- [0032]) connected between the anode (i.e., such as anode terminal 110/PAD; see for example fig. 1, para. [0021]- [0032]) and the gate (i.e., such as gate G/124-2; see for example fig. 1, para. [0021]- [0032]); and a resistor (i.e., such as resistor 128; see for example fig. 1, para. [0021]- [0032]) connected between the gate (i.e., such as gate G/124-2; see for example fig. 1, para. [0021]- [0032]) and the cathode (i.e., such as cathode terminal 112/GND; see for example fig. 1, para. [0021]- [0032]).
Regarding claim 16, is rejected for the same reasons that have already been stated/discussed above in rejected claim 1. {See rejection of claim 1}
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Wang (US Publication No. 20150236500) in view of Metz et al (US Patent No. 5452171).
Regarding claim 10, Wang discloses the device (i.e., such as device 100; see for example fig. 1, para. [0021]- [0032]).
Wang does not explicitly disclose further comprising a resistor connected between the at least one first n+ region and the FET.
Metz discloses and ESD IC (i.e., see for example fig. 5b, Col. 6 lines 8+); wherein a resistor (i.e., such as resistor 48; see for example fig. 5b, Col. 6 lines 8+) connected between the at least one first n+ region (i.e., such as n+ regions; see for example fig. 5b, Col. 6 lines 8+) and the FET (i.e., such as FET 18; see for example fig. 5b, Col. 6 lines 8+).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the resistor in Wang, as taught by Metz, as it provides the advantage of optimizing the circuit design towards reducing component size, enabling high-density packaging, and boosting performance by lowering parasitic inductance and capacitance.
Allowable Subject Matter
Claims 2-9, 13-15 and 17-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2, Wang teaches the invention set forth above. However, Wang does not particularly teach wherein the base of the first PNP BJT corresponds to a first n-well in which the plurality of first p+ regions and the at least one first n+ region are disposed and the first n-well extending in the first direction, and wherein the collector of the first PNP BJT corresponds to a p-well adjacent to the first n-well in a second direction crossing the first direction and the p-well extending in the first direction.
Hence claim 2 will be deemed allowable if rewritten in an independent form.
Claims 3-7 depend on objected claim 2, consequently claims 3-7 will also be deemed allowable.
Regarding claim 8, Wang teaches the invention set forth above. However, Wang does not particularly teach wherein a first sum of lengths of the plurality of first p+ regions in the first direction is greater than a second sum of at least one length of the at least one first n+ region in the first direction.
Hence claim 8 will be deemed allowable if rewritten in an independent form.
Regarding claim 9, Wang teaches the invention set forth above. However, Wang does not particularly teach wherein a first sum of lengths of the plurality of first p+ regions in the first direction is less than a second sum of at least one length of the at least one first n+ region in the first direction.
Hence claim 9 will be deemed allowable if rewritten in an independent form.
Regarding claim 13, Wang teaches the invention set forth above. However, Wang does not particularly teach wherein the FET is a p-channel field effect transistor (PFET), wherein the PFET comprises: a gate electrically connected to the anode; a drain electrically connected to the cathode; and a source connected to the at least one first n+ region.
Hence claim 13 will be deemed allowable if rewritten in an independent form.
Claim 14 depends on objected claim 13, consequently claim 14 will also be deemed allowable.
Regarding claim 15, Wang teaches the invention set forth above. However, Wang does not particularly teach wherein each of the plurality of first p+ regions and the at least one first n+ region are disposed between two adjacent gate electrodes extending in a second direction crossing the first direction.
Hence claim 15 will be deemed allowable if rewritten in an independent form.
Regarding claim 17, Wang teaches the invention set forth above. However, Wang does not particularly teach wherein the base of the first NPN BJT corresponds to a p-well in which the plurality of n+ regions and the at least one p+ region are disposed and the p-well extending in the first direction, and wherein the collector of the first NPN BJT corresponds to a first n-well adjacent to the p-well in a second direction crossing the first direction and the first n-well extending in the first direction.
Hence claim 17 will be deemed allowable if rewritten in an independent form.
Claim 18 depends on objected claim 17, consequently claim 18 will also be deemed allowable.
Claims 31-32 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 31, Wang (US Publication No. 20150236500) does not teach or suggest a device comprising: a p-well extending in a first direction; a first n-well adjacent to the p-well in a second direction crossing the first direction and, the first n-well extending in the first direction; a first n+ region electrically connected to a cathode node and disposed in the p-well; a first p+ region electrically connected to the cathode node and disposed in the p-well; a plurality of second p+ regions electrically connected to an anode node, the plurality of second p+ regions being spaced apart from each other in the first direction in the first n-well; and at least one second n+ region electrically connected to a field effect transistor that is electrically connected to the cathode node or the anode node, the at least one second n+ region being disposed between the plurality of second p+ regions in the first n-well.
Claim 32 is allowed, as it depends on allowed claim 31.
Claims 19-30 and 33-46 are cancelled.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUAAMAR Q AL-TAWEEL whose telephone number is (571)270-0339. The examiner can normally be reached 0730-1700.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V Tran can be reached at (571) 270- 1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MUAAMAR QAHTAN AL-TAWEEL/Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838