DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
The following claim(s) is/are pending in this office action: 1-20
The following claim(s) is/are amended: 1-2, 4-7, 10
The following claim(s) is/are cancelled: -
The following claim(s) is/are new: 13-20
Claim(s) 1-20 is/are rejected. This rejection is FINAL.
Previous Rejections Withdrawn
The Double Patenting rejection to claim(s) 1-12 is/are withdrawn based on the amendment.
The 35 USC 112(b)/(d) rejection to claim(s) 1-6, 12 is/are withdrawn based on the amendment.
Response to Arguments
Applicant’s arguments filed in the amendment filed 4/8/2026, have been fully considered but are moot in view of new grounds of rejection. The reasons set forth below.
Applicant’s Invention as Claimed
Claim Rejections - 35 USC § 103
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 5-8 and 13-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ching (US Pub. 2005/0165970) in view of Bains (US Pub. 2007/0130374) and further in view of Zavesky (US Pub. 2019/0190848).
With respect to Claim 1, Ching teaches a chip module, comprising: (Fig. 1, para. 28; electronic component 110 can be an integrated circuit)
a plurality of first ports, (The contacts being within a plurality of ports will be taught later. para. 38; plurality of contacts 116 such as a pin)
wherein at least some of the plurality of first ports are first selection ports that can be configured as a read port or a write port; (Write/read ports will be taught later. paras. 38-42; contacts create signal lines which can include transmission and reception signal lines to transmit to or receive from component 120)
a memory; and a processor operatively coupled to the memory to: (paras. 28-29; processor and memory)
obtain a required quantity of write ports and a required quantity of read ports, and compare the required quantity of write ports and the required quantity of read ports with a current quantity of write ports and a current quantity read ports, to determine whether at least one first selection port needs to be switched. (para. 47; Bandwidth allocation control logic generates control signals to configure interfaces. Paras. 51-52; BAC logic defines how many transceivers are configured for transmit and how many are configured for reception (such as ½ transmit, ½ receive or ¾ transmit, ¼ receive) and sends control signals to configure the transceivers appropriately. The configuration may be made based on received/transmitted packets. Para. 57; Absolute values or min/max values for transceivers operating in a particular mode. Para. 59; a ½ transmit, ½ receive interface then makes a determination as to the intended configuration of the interface, and an appropriate number of transceivers are configured. Paras. 62-64; controlling number of write interfaces based on transmit queue depth.)
But Ching does not explicitly teach a plurality of first ports.
Bains, however, does teach a plurality of first ports (Fig. 3, para. 33; plurality of ports creating a plurality of interconnects between devices.)
Read port or a write port (para. 22; data port may be for write or read transactions.)
It would have been obvious to one of ordinary skill prior to the effective filing date to combine the chip module of Ching with the plurality of ports in order to control multiple ports to meet bandwidth needs. (Bains, para. 26)
But modified Ching does not explicitly teach a future time period.
Zavesky, however, does teach for a future time period based on a service requirement; for the future time period (paras. 19, 33; system can predict that the data rate for a scheduled service will be unacceptable and can increase the data rate for the time scheduled. para. 42, 52; system predicts future usage. paras. 31, 46-47; QoS rules such as minimum/maximum bandwidth rates set for particular services or particular times of day. para. 66; management of network based on predictions and QoS.
It would have been obvious to one of ordinary skill prior to the effective filing date to combine the chip module of modified Ching with the future time period in order to create a more flexible service by allowing temporary or dynamic management of bandwidth. (Zavesky, paras. 15-18)
With respect to Claim 2, modified Ching teaches the chip module according to claim 1, and Ching also teaches wherein the processor is further to: determine that at least one first selection port needs to be switched, (Paras. 51-52; BAC logic defines how many transceivers are configured for transmit and how many are configured for reception (such as ½ transmit, ½ receive or ¾ transmit, ¼ receive) and sends control signals to configure the transceivers appropriately. The configuration may be made based on received/transmitted packets. Para. 57; Absolute values or min/max values for transceivers operating in a particular mode. Para. 59; a ½ transmit, ½ receive interface then makes a determination as to the intended configuration of the interface, and an appropriate number of transceivers are configured.)
and switch the at least one first selection port based on the required quantity of write ports and the required quantity of read ports. (paras. 51-52, 57, 59; reconfiguration where the number of transceivers only transmitting or only receiving is reallocated.)
With respect to Claim 3, modified Ching teaches the chip module according to claim 1, and Ching also teaches wherein each of the at least one first selection port comprises: a first connection port, (para. 38; contact 116a)
a first receiving circuit, a first sending circuit, (para. 40; transceiver 115a includes both transmit and receive circuits)
and a first selector switch; the first connection port is connected to one of the first receiving circuit and the first sending circuit by using the first selector switch; (paras. 40, 47; BAC logic sends control signals to a programmable register for the transceivers which determines the mode of operation for the transceiver.)
when the first receiving circuit is connected to the first connection port, the first selection port is configured as a write port; and when the first sending circuit is connected to the first connection port, the first selection port is configured as a read port. (para. 41-42; transmit and receive modes.)
With respect to Claim 5, Ching teaches a communication system, comprising: a first chip module and a second chip module, (Fig. 1, para. 28; Electronic components 110/120. Electronic component 110 can be an integrated circuit.)
wherein the first chip module comprises: a plurality of first ports, (The contacts being within a plurality of ports will be taught later. para. 38; plurality of contacts such as a pin)
wherein at least some of the plurality of first ports are first selection ports that can be configured as a read port or a write port, (Write/read ports will be taught later. paras. 38-42; contacts create signal lines which can include transmission and reception signal lines to transmit to or receive from component 120)
a memory; and a processor operatively coupled to the memory to: (paras. 28-29; processor and memory)
obtain a required quantity of write ports and a required quantity of read ports, and compare the required quantity of write ports and the required quantity of read ports with a current quantity of write ports and a current quantity read ports, to determine least one first selection port that needs to be switched; (para. 47; Bandwidth allocation control logic generates control signals to configure interfaces. Paras. 51-52; BAC logic defines how many transceivers are configured for transmit and how many are configured for reception (such as ½ transmit, ½ receive or ¾ transmit, ¼ receive) and sends control signals to configure the transceivers appropriately. The configuration may be made based on received/transmitted packets. Para. 57; Absolute values or min/max values for transceivers operating in a particular mode. Para. 59; a ½ transmit, ½ receive interface then makes a determination as to the intended configuration of the interface, and an appropriate number of transceivers are configured. Paras. 62-64; controlling number of write interfaces based on transmit queue depth.)
wherein the first ports of the first chip module and a plurality of second ports of the second chip module are connected in a one-to-one correspondence. (Fig. 1, para. 39; signal lines are the connections between 116a-n and 126a-n)
But Ching does not explicitly teach a plurality of ports.
But Ching does not explicitly teach a plurality of first ports.
Bains, however, does teach a plurality of first ports (Fig. 3, para. 33; plurality of ports creating a plurality of interconnects between devices.)
Read port or a write port (para. 22; data port may be for write or read transactions.)
It would have been obvious to one of ordinary skill prior to the effective filing date to combine the system of Ching with the plurality of ports in order to control multiple ports to meet bandwidth needs. (Bains, para. 26)
But modified Ching does not explicitly teach a future time period.
Zavesky, however, does teach for a future time period based on a service requirement; for the future time period (paras. 19, 33; system can predict that the data rate for a scheduled service will be unacceptable and can increase the data rate for the time scheduled. para. 42, 52; system predicts future usage. paras. 31, 46-47; QoS rules such as minimum/maximum bandwidth rates set for particular services or particular times of day. para. 66; management of network based on predictions and QoS.
It would have been obvious to one of ordinary skill prior to the effective filing date to combine the system of modified Ching with the future time period in order to create a more flexible service by allowing temporary or dynamic management of bandwidth. (Zavesky, paras. 15-18)
With respect to Claim 6, modified Ching teaches the communication system according to claim 5, and Ching also teaches wherein the processor comprises a first processor, the memory comprises a first memory, (paras. 28-29; processor and memory.)
at least some of the plurality of second ports are second selection ports, (paras. 38-42; plurality of contacts 126 where the contacts create signal lines which can include transmission and reception signal lines to transmit to or receive from component 110)
and the second chip module further comprises, a second memory; and a second processor operatively coupled to the second memory to: (paras. 28-29; processor and memory. Fig. 1, para. 40; control signals sent to both electronic components. Para. 47; BAC may be included in either component or may be implemented in a virtual manner. Therefore, it would have been obvious to one of ordinary skill prior to the effective filing date to separate the functionality of the control of both components 110/120 and instead have each component have its own BAC with similar control logic to control its component. Making separable is obvious, see MPEP 2144.04.)
control, based on a transmit/receive requirement of a peer chip module paired with the second chip module, (paras. 51-52; reconfiguration of transceivers. paras. 40, 47; Transceiver 115a includes both transmit and receive circuits. BAC logic sends control signals to a programmable register for the transceivers which determines the mode of operation for the transceiver. Fig. 1, para. 40; control signals sent to both electronic components. Para. 28; electronic component 110 may be a master device.)
at least one second selection port to be switched to a read port or a write port. (paras. 51-52, 57, 59; reconfiguration where the number of transceivers only transmitting or only receiving is reallocated.)
With respect to Claim 7, Ching teaches a port allocation method, comprising: obtaining a required quantity of write ports and a required quantity of read ports; and comparing the required quantity of write ports and the required quantity of read ports with a current quantity of write ports and a current quantity of read ports, to determine whether at least one first selection port needs to be switched; (The application to write/read ports will be taught later. para. 47; Bandwidth allocation control logic generates control signals to configure interfaces. Paras. 51-52; BAC logic defines how many transceivers are configured for transmit and how many are configured for reception (such as ½ transmit, ½ receive or ¾ transmit, ¼ receive) and sends control signals to configure the transceivers appropriately. The configuration may be made based on received/transmitted packets. Para. 57; Absolute values or min/max values for transceivers operating in a particular mode. Para. 59; a ½ transmit, ½ receive interface then makes a determination as to the intended configuration of the interface, and an appropriate number of transceivers are configured. Paras. 62-64; controlling number of write interfaces based on transmit queue depth.)
and switching the at least one first selection port of a chip module to a read port or a write port. (paras. 51-52, 57, 59; reconfiguration where the number of transceivers only transmitting or only receiving is reallocated.)
But Ching does not explicitly teach ports.
Bains, however, does teach ports (Fig. 3, para. 33; plurality of ports creating a plurality of interconnects between devices.)
Write ports, read ports (para. 22; data port may be for write or read transactions.)
It would have been obvious to one of ordinary skill prior to the effective filing date to combine the method of Ching with the plurality of ports in order to control multiple ports to meet bandwidth needs. (Bains, para. 26)
But modified Ching does not explicitly teach a future time period.
Zavesky, however, does teach for a future time period based on a service requirement; for the future time period (paras. 19, 33; system can predict that the data rate for a scheduled service will be unacceptable and can increase the data rate for the time scheduled. para. 42, 52; system predicts future usage. paras. 31, 46-47; QoS rules such as minimum/maximum bandwidth rates set for particular services or particular times of day. para. 66; management of network based on predictions and QoS.
It would have been obvious to one of ordinary skill prior to the effective filing date to combine the method of modified Ching with the future time period in order to create a more flexible service by allowing temporary or dynamic management of bandwidth. (Zavesky, paras. 15-18)
With respect to Claim 8, it is substantially similar to Claim 2, and is rejected in the same manner, the same art and reasoning applying.
With respect to Claim 13, modified Ching teaches the chip module according to claim 1, and Ching also teaches wherein the processor is further to: determine to-be-received data is queued; determine a selection port of the first selection ports that is configured as a write port is idle; and switch the selection port of the first selection ports to a read port. (Paras. 62-64; configuration of interfaces based upon number of queued data packets. para. 40; disabled mode of operation for transceiver. Para. 41; change of mode to receive. It would have been obvious to one of ordinary skill prior to the effective filing date to change disabled transceivers to receive in order to have a receiver for clearing out the queued packets.)
With respect to Claim 14, modified Ching teaches the chip module according to claim 1, and Ching also teaches wherein the service requirement is indicated by an upper-layer chip or software. (para. 40; bandwidth allocation control logic controls status of ports.)
With respect to Claim 15, modified Ching teaches the chip module according to claim 1, and Ching also teaches wherein the processor is further to: obtain locations of the required quantity of write ports and the required quantity of read ports; and compare locations of the required quantity of write ports and read ports to current locations of the write ports and read ports to determine a selection port of the first selection ports needs to be switched. (para. 47-48, 51; BAC sends control signals to both sets of transceivers 115a-n and 125a-n and interfaces 119 and 129. Para. 52; control of both sets of interfaces based on utilization.)
and Bains also teaches locations (Examiner notes that Ching teaches this feature because it addresses both interfaces, and therefore distinguishes between transceivers located on the first interface and those located on the second interface. Regardless, Examiner will also cite Bains. paras. 19-22; system can individually configure, command and address individual ports.)
The same motivation to combine as the independent claim applies here.
With respect to Claim 16, modified Ching teaches the chip module according to claim 1, and Ching also teaches wherein the processor is further to: when a current ratio of write ports to read ports is less than a target ratio, control at least some of the first selection ports acting as read ports to be switched to write ports; or when the current ratio is greater than the target ratio, control at least some of the first selection ports acting as write ports to be switched to read ports. (paras. 27, 52; ratio of transmit to receive packets in order to control transmit/receive profile. Reconfiguring from ½ transmit, ½ receive to ¾ transmit and ¼ receive. Further, Examiner notes that a ratio is simply a different way of describing absolute values of modes, see para. 57; absolute and min/max amounts of operation. Therefore, it would have been obvious to one of ordinary skill prior to the effective filing date to describe the configuration in terms of ratios rather than absolute values because ratios are a substitute known method of describing states. paras. 51-52, 57, 59; reconfiguration where the number of transceivers only transmitting or only receiving is reallocated.)
With respect to Claims 17-20, they are substantially similar to Claims 14-16, 13, respectively, and are rejected in the same manner, the same art and reasoning applying.
Claims 4 and 9-12 are rejected under 35 U.S.C. 103(a) as being unpatentable over Ching (US Pub. 2005/0165970) in view of Bains (US Pub. 2007/0130374) in view of Zavesky (US Pub. 2019/0190848) and further in view of Pandey (US Pub. 2008/0275975).
With respect to Claim 4, modified Ching teaches the chip module according to claim 1, and Ching also teaches wherein the processor is further to: send a switching indication message to a peer chip module paired with the chip module, (paras. 51-52; reconfiguration of transceivers. paras. 40, 47; Transceiver 115a includes both transmit and receive circuits. BAC logic sends control signals to a programmable register for the transceivers which determines the mode of operation for the transceiver. Fig. 1, para. 40; control signals sent to both electronic components. Para. 28; electronic component 110 may be a master device.)
But modified Ching does not explicitly teach a completion indication message.
Pandey, however, does teach and receive a switching completion indication message fed back by the peer chip module. (paras. 83-84, 91; periodic port status message that indicates the status of a port. It would have been obvious to one of ordinary skill prior to the effective filing date to include a configuration of the port as a status of the port in order to confirm to the control algorithm what ports are transmitting/receiving to allow for proper port allocation calculation.)
It would have been obvious to one of ordinary skill prior to the effective filing date to combine the chip module of modified Ching with the port status message in order to report the port status to other devices.
With respect to Claim 9, it is substantially similar to Claim 4, and is rejected in the same manner, the same art and reasoning applying.
With respect to Claim 10, modified Ching teaches the port allocation method according to claim 7, and Ching also teaches further comprising: when a current ratio of write ports to read ports is less than a target ratio, controlling at least some of first selection ports acting as read ports to be switched to write ports; or when the current ratio is greater than the target ratio, controlling at least some of the first selection ports acting as write ports to be switched to read ports. (paras. 27, 52; ratio of transmit to receive packets in order to control transmit/receive profile. Reconfiguring from ½ transmit, ½ receive to ¾ transmit and ¼ receive. Further, Examiner notes that a ratio is simply a different way of describing absolute values of modes, see para. 57; absolute and min/max amounts of operation. Therefore, it would have been obvious to one of ordinary skill prior to the effective filing date to describe the configuration in terms of ratios rather than absolute values because ratios are a substitute known method of describing states. paras. 51-52, 57, 59; reconfiguration where the number of transceivers only transmitting or only receiving is reallocated.)
With respect to Claim 11, it is substantially similar to Claim 3, and is rejected in the same manner, the same art and reasoning applying.
With respect to Claim 12, it is substantially similar to Claim 4, and is rejected in the same manner, the same art and reasoning applying.
Remarks
Applicant argues at Remarks, pg. 7 that the terminal disclaimer fixes the Double Patenting issue and that amendments to Claims 1-6 and 12 fix the 112(b) and 112(d) rejections. Examiner agrees and withdraws all these rejections.
Applicant argues at Remarks, pg. 8-9 that Ching and Bains do not teach the amended independent claims. Examiner does not read the complaint as targeting any prior teachings, but simply that the combination does not teach the newly amended future time period analysis. Examiner agrees the combination does not teach future time period analysis and cites new art to teach. The new claims are taught above.
All claims remain rejected.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/NICHOLAS P CELANI/Examiner, Art Unit 2449
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