DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
2. Claims 1, 4-5, 7 and 9 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chiu et al. U.S. Patent Application Publication 2018/0366429 A1 (the ‘429 reference).
The reference discloses in Fig. 1 and related text a semiconductor packaged as claimed.
Referring to claim 1, the ‘429 reference discloses a semiconductor package, comprising:
a first semiconductor device (124(3), para [74] (paragraph(s) [0074])) in a first area;
a second semiconductor device (124(2)) in a second area; and
a plurality of interconnections (126(3), 126(4), 128, para [78, 79]) comprising a command-and-address (CA) vertical interconnection, a data input-output vertical interconnection, a memory management vertical interconnection, a power vertical interconnection, and a ground vertical interconnection (para [79]: “vertical signal paths or traces of the vertical interconnection portion 128, the dies 114 may be configured to communicate signals, power, and/or ground between each other and also with the fan-out dies 124”, para [84]: “for memory applications, one of the fan-out dies 124, such as the first fan-out die 124(1), may be a controller that is configured to control and/or manage various memory operations”, emphases added),
wherein the CA vertical interconnection, the data input-output vertical interconnection, the memory management vertical interconnection, the power vertical interconnection, and the ground vertical interconnection (126(3), 126(4), 128) are laterally spaced apart from the first semiconductor device (124(3)), and
wherein the power vertical interconnection and the ground vertical interconnection (126(3), 126(4), 128) are not between the first semiconductor device (124(3)) and the second semiconductor device (124(2)).
Referring to claim 4, the reference further discloses that:
the first semiconductor device (124(3)) includes a first side surface (right side surface) and a second side surface (left side surface) parallel to the first side surface, the second side surface (the left side surface of 124(3)) facing the second semiconductor device (124(2)), and
at least one of the CA vertical interconnection, the data input-output vertical interconnection, and the memory management vertical interconnection (126(4), 128) is adjacent to the first side surface (the right surface of 124(3)).
Referring to claim 5, the reference further discloses that:
the second semiconductor device (124(2)) includes a first side (right side) facing the first semiconductor device (124(3)) and a second side (left side) opposite to the first side, and
at least one of the power vertical interconnection and the ground vertical interconnection (126(3)) is among side surfaces of the second semiconductor device (124(2)) on a portion facing the second side (the left side of 124(2)).
Referring to claim 7, the reference further discloses that the first semiconductor device (124(3)) is an application processor (AP) chip and the second semiconductor device (124(2)) is a power management integrated circuit chip (para [88]: “FIG. 1 shows three accessory dies 124(1), 124(2), 124(3) for illustration purposes, although any number of accessory dies in various configurations may be disposed between the first and second RDL 106, 122 so that the fan-out portion 104 includes a complete set of accessory dies for the non-volatile memory system 100”).
Referring to claim 9, the reference further discloses that the first semiconductor device (124(3)) and the second semiconductor device (124(2)) are on a lower package substrate (106, para [80]) and are encapsulated by an encapsulation material (127, para [78]).
3. Claims 13, 15-16 and 18-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. U.S. Patent Application Publication 20170110413 A1 (the ‘413 reference).
The reference discloses in Fig. 14 and related text a semiconductor packaged as claimed.
Referring to claim 13, the ‘413 reference discloses a semiconductor package, comprising:
a first semiconductor device (200, 220, para [15, 22]) in a first area;
a second semiconductor device (another 200, 220) in a second area; and
a plurality of interconnections (interconnect vias 114, 124, para [10, 13, 15, 22]) comprising a command-and-address (CA) vertical interconnection, a data input-output vertical interconnection, and a memory management vertical interconnection (para [15]: “The interconnect structure electrically connects various active devices to form functional circuits within die 200. The functions provided by such circuits may include memory structures, processing structures, sensors, amplifiers, power distribution, input/output circuitry, or the like”, para [22]: “Dies 200 and 220 may perform a same or different functions”),
wherein at least one of the CA vertical interconnection, the data input-output vertical interconnection, and the memory management vertical interconnection (114, 124) is between the first semiconductor device (200, 220) and the second semiconductor device (the another 200, 220), and
wherein the CA vertical interconnection, the data input-output vertical interconnection, and the memory management vertical interconnection (114, 124) are laterally spaced apart from the first semiconductor device (200, 220).
Referring to claim 15, the reference further discloses an upper redistribution layer (fan-out RDL 118, para [22]) and a lower redistribution (128),
wherein the at least one of the CA vertical interconnection, the data input-output vertical interconnection, and the memory management vertical interconnection (124) between the first semiconductor device (220) and the second semiconductor device (the another 220) is a via structure (TIV) electrically connecting the upper redistribution layer (118) to the lower redistribution layer (128).
Referring to claim 16 and using the same reference characters, interpretations, and citations as detailed above for claim 13 where applicable, the reference discloses a semiconductor package, comprising:
a first semiconductor device (200, 220) in a first area;
a second semiconductor device (another 200, 220) in a second area; and
a plurality of interconnections (114, 124) comprising a data input-output vertical interconnection, a memory management vertical interconnection, a power vertical interconnection, and a ground vertical interconnection,
wherein the data input-output vertical interconnection, and the memory management vertical interconnection (114, 124) are adjacent to the first semiconductor device (200, 220),
wherein at least one of the data input-output vertical interconnection, and the memory management vertical interconnection (114, 124) is between the first semiconductor device and the second semiconductor device, and
wherein the data input-output vertical interconnection, the memory management vertical interconnection, the power vertical interconnection, and the ground vertical interconnection (114, 124) are laterally spaced apart from the first semiconductor device (200, 220).
Referring to claim 18, the reference further discloses that:
the first semiconductor device (200) includes a first side surface (right side surface) and a second side surface (left side surface) parallel to the first side surface, the second side surface facing the second semiconductor device (the another 200), and the data input-output vertical interconnection (114) is adjacent to the first side surface (the right side surface).
Referring to claim 19, the reference further discloses that:
the second semiconductor device (the another 200) includes a first side (right side) facing the first semiconductor device (200) and a second side (left side) opposite to the first side, and
at least one of the power vertical interconnection and the ground vertical interconnection (114) is among side surfaces of the second semiconductor device on a portion facing the second side.
Allowable Subject Matter
4. Claims 2-3, 6, 8, 10-12, 14, 17 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for the indication of allowable subject matter: The cited art, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fails to teach or render obvious a semiconductor package with all exclusive limitations as recited in claims 2-3, 6, 8, 10, 14, 17 and 20, which may be characterized (claim 2) in that at least one of the data input-output vertical interconnection and the memory management vertical interconnection is between the first semiconductor device and the second semiconductor device, (claim 3) at least one of the CA vertical interconnection and the data input-output vertical interconnection is between the first semiconductor device and the second semiconductor device, (claims 6 and 20) in a dummy vertical interconnection, the dummy vertical interconnection not being between the first semiconductor device and the second semiconductor device, (claim 8) in that the CA vertical interconnection, the data input-output vertical interconnection, the memory management vertical interconnection, the power vertical interconnection, and the ground vertical interconnection have a regular arrangement of equilateral triangles, (claim 10) in that the second semiconductor device includes a first side facing the first semiconductor device and a second side opposite to the first side, and the CA vertical interconnection, the data input-output vertical interconnection, the memory management vertical interconnection, the power vertical interconnection, and the ground vertical interconnection are not, among side surfaces of the second semiconductor device, on a side surface facing the second side, (claim 14) in a power vertical interconnection, and a ground vertical interconnection, and in that the CA vertical interconnection, the data input-output vertical interconnection, the memory management vertical interconnection, the power vertical interconnection, and the ground vertical interconnection are not, among side surfaces of the second semiconductor device, on a portion facing a side opposite to a side facing the first semiconductor device, and (claim 17) in that the power vertical interconnection and the ground vertical interconnection are not between the first semiconductor device and the second semiconductor device.
Conclusion
5. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TU TU V HO whose telephone number is (571)272-1778. The examiner can normally be reached on Monday to Thursday 6:30 - 15:00, Monday through Thursday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff W Natalini can be reached on 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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07-23-2026
/TU-TU V HO/Primary Examiner, Art Unit 2818
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