Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1. Claims 1-8, 15 and 17-27 are pending in the application including newly added claims 21-27.
Election/Restriction
2. Applicant’s election of Species 1 (claims 1-8, 15 and 17) is acknowledged.
Newly submitted claims 24 and 25 are directed to an invention that is independent or distinct from the invention originally claimed for the following reasons: wherein the bitline segments are electrically shorted together using conductive shunts of claim 24; and a first portion of the memory array has a double bitline configuration using the multi-pillar memory cells, and a second portion of the memory array has a single bitline configuration using single pillar memory cells; and the controller is configured to select the first or second portion to use during multiplication in claim 25.
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits.
Accordingly, the claims 24 and 25 are withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP 821.03.
However, the claims 24 and 25 will be rejoined upon the indication of allowable subject matter of its independent claim 22.
Claim Rejections - 35 USC § 102
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
4. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
5. Claims 1-2, 15, 21-23 and 26 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by Kondo US Pub. No. 20230084863.
As per claims 1-2, 22 and 26 Figs. 1 and 5 of Kondo is directed to a device comprising: at least one first pillar (a first CV in a left of SHE connecting to MP and 25(BL), par. 79)) of transistors (MT0-MT7) ; at least one second pillar (a second CV in a right of SHE connecting to MP and 25(BL), par. 79)) of transistors (MT0-MT7), and a bitline (25(BL)) overlying the first and second pillars, wherein each of the first and second pillars is electrically connected to the bitline (through CV, par. 80).
As per claim 15, Figs. 3 and 5 of Kondo disclose wherein the at least one first pillar includes first pillars (CVs connecting to 25(BL)configured in a first row (WL0); the at least one second pillar includes second pillars (other CVs connecting to another BL, Fig. 3)configured in a second row (WL1); and the bitline (BL) is formed overlying the first and second rows (Fig. 3, par. 58).
As per claim 21, Fig. 5 of Kondo discloses further comprising select transistors (ST1s), wherein each of the first and second pillars is electrically connected (through CV, par. 80) to the bitline by the select transistors.
As per claim 23, Fig. 3 or 5 of Kondo discloses wherein the bitline includes bitline segments (between MPs) that are electrically connected.
Claim Rejections - 35 USC § 103
6. The following is a quotation of 35 U.S.C. § 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
7. Claim 3 is rejected under 35 U.S.C. § 103(a) as being unpatentable over Kondo US Pub. No. 20230084863 in view of Lin et al. US Pub. No. 20210242239 and further in view of Grobis et al US Pub. No. 20220108158.
Fig. 5 of Kondo discloses further comprising a wordline (WL0) configured to select a first memory cell (MT0) but fails to disclose (1) wherein the wordline is connected to gates of the respective first and second transistors of the first memory cell, and (2) wherein the bitline is configured to accumulate an output current from the first memory cell.
However, Fig. 11 and a paragraph 58 of Lin disclose the wordline (WL) is connected to gates of the respective first and second transistors (Fig. 11, par. 58) of the first memory cell (Fig. 11). It would have been obvious to a person of ordinary skill in the art at the time invention was made to modify Kondo’s memory cell which utilizes the two transistors as taught by Lin in order to form these two transistor in parallel to share the same wordline (par. 58).
However, Fig. 13 and a paragraph 85 of Grobis disclose wherein the bitline (BL, par. 85) is configured to accumulate an output current (I1, par. 85) from the first memory cell (M1,1). It would have been obvious to a person of ordinary skill in the art at the time invention was made to modify Kondo’s memory cell which utilizes an accumulator for outputting current as taught by Grobis in order to perform operations such as accumulations for multiply and accumulation operations (par. 85).
As per claim 7, Kondo fails to disclose (1) wherein each memory cell is programmed to store the weight, and (2) the first and second transistors of the memory cell are programmed in parallel.
However, Fig. 11 and 13 of Grobis disclose wherein each memory cell is programmed to store the weight (par. 23). It would have been obvious to a person of ordinary skill in the art at the time invention was made to modify Kondo’s memory cells which utilizes to program the memory cell to store weight as taught by Grobis in order to allow for using the weights of the layers for a neutral network (par. 23).
However, Fig. 11 and a paragraph 58 of Lin disclose the first and second transistors of the memory cell (Fig. 11) are programmed in parallel. It would have been obvious to a person of ordinary skill in the art at the time invention was made to modify Kondo’s memory cell which utilizes the two transistors as taught by Lin in order to program in parallel since these parallel transistors to share the same wordline WL, the source line SL and the bitline BL (par. 58).
As per claim 8, Kondo fails to disclose (1) wherein the first and second transistors of each memory cell are programmed (2) to store a respective weight so that a sum of output currents from the first and second transistors corresponds to a target current for the respective weight.
However, Fig. 11 and a paragraph 58 of Lin disclose the first and second transistors of the memory cell (Fig. 11) are programmed. It would have been obvious to a person of ordinary skill in the art at the time invention was made to modify Kondo’s memory cell which utilizes the two transistors as taught by Lin in order to program in parallel since these parallel transistors to share the same wordline WL, the source line SL and the bitline BL (par. 58).
However, Fig. 11 and 13 of Grobis disclose to store a respective weight (weight matrix, Fig. 11) so that a sum of output currents (I1-I3 , par. 85) from the first and second transistors corresponds to a target current (Fig. 11 or Fig. 13) for the respective weight. It would have been obvious to a person of ordinary skill in the art at the time invention was made to modify Kondo’s memory cell which utilizes to store weights in the memory cells as taught by Grobis in order to generate in a training or learning phase at the output for a neural network (par. 1 or 7).
8. Claims 4-6, 17-20, and 27 are rejected under 35 U.S.C. § 103(a) as being unpatentable over Kondo US Pub. No. 20230084863 in view of Grobis et al US Pub. No. 20220108158.
As per claims 4, 6, and 27, Fig. 5 of Kondo discloses wherein each of the first and second pillars is electrically connected to the bitline by select transistors (MT0s) and gates (by WL0) of the select transistors, but fails to disclose at least one input pattern for multiplication including a weight (reciting in a claim 6) is applied to gates of the select transistors. However, Figs. 10-11 and 13 and a paragraphs 69 and 70 of Grobis disclose at least one input pattern for multiplication including a weight (Fig. 10 or 11) is applied to gates (as input) of the select transistors (for a NAND memory device, par. 72). It would have been obvious to a person of ordinary skill in the art at the time invention was made to modify Kondo’s memory cell which utilizes an input pattern for multiplication as taught by Grobis in to generate in a training or learning phase at the output for a neural network (par. 1 or 70). It is noted that a block 102 of Fig. 1 of Grobis discloses a limitation a controller in a claim 27.
As per claim 5, Kondo fails to disclose further comprising an accumulator to accumulate memory cell output currents for a multiplication and provide a digital result of the multiplication. However, Fig. 13 and a paragraph 85 of Grobis disclose an accumulator (ADC 1313) to accumulate memory cell output currents (I1-I3 , par. 85)for a multiplication and provide a digital result (1315) of the multiplication. It would have been obvious to a person of ordinary skill in the art at the time invention was made to modify Kondo’s memory cell which utilizes an accumulator for outputting current as taught by Grobis in order to perform operations such as accumulations for multiply and accumulation operations (par. 85).
As per claims 17, Figs. 1 and 5 of Kondo disclose an apparatus comprising: a host interface (connecting between 100 and 1, Fig. 1, par. 34); and a memory cell array (11) comprising memory cells (Fig. 2)
Kondo fails to disclose memory cells configured to store weights received from the host. However, Figs. 1 and 11 of Grobis disclose a memory cell array (104, par. 26) comprising memory cells (Fig. 13) configured to store weights (Fig. 11) received from the host (120, par. 24). It would have been obvious to a person of ordinary skill in the art at the time invention was made to modify Kondo’s memory cells which utilizes to store weights as taught by Grobis in order to generate in a training or learning phase at the output for a neural network (par. 1 or 70).
As per claim 18, Kondo fails to disclose the limitations in the claim 18. However, Figs. 1 and 11 of Grobis disclose these limitations as further comprising logic circuitry (102)configured to: receive, via the host interface (126) from the host (122), first weights for a neural network (weight matrix, Fig. 11); program first memory cells (M1-1-M1-3, Fig. 13) to store the first weights (par. 23); and perform multiplication (Fig. 11) of the first weights by first inputs by summing output currents (I1-I3 , par. 85) from the first memory cells. It would have been obvious to a person of ordinary skill in the art at the time invention was made to modify Kondo’s memory cells which utilizes to store weights in the memory cells as taught by Grobis in order to generate in a training or learning phase at the output for a neural network (par. 1 or 70).
As per claim 19, Figs. 3 and 5 of Kondo disclose wherein the access lines are bitlines overlying the pillars (par. 59).
As per claim 20, Figs. 1 and 5 of Kondo disclose wherein each memory cell of the array includes respective transistors (MT0 and Mt1) from at least two respective pillars (MPs adjacent to SHE) located in adjacent rows of the pillars, the apparatus further comprising sensing circuitry (13, par. 42)) coupled to the bitlines and configured to measure output currents from the memory cells.
9. When responding to the office action, Applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner to locate the appropriate paragraphs.
10. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the date of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
11. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Hoai V. Ho whose telephone number is (571) 272-1777. The examiner can normally be reached 7:00 AM -- 5:30 PM from Monday through Thursday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached on (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is (571)-273-8300.
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/HOAI V HO/Primary Examiner, Art Unit 2827