DETAILED ACTION
The present application, filed 06/04/2024, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Drawings
Figure 1 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 2, 6, 7, 11, 15-17, and 20 are objected to because of the following informalities:
Re claim 2, it appears that “the difference” (lines 3-4, 7) should be “a difference”. It appears that “the voltage” (last line) should be “a voltage”.
Re claim 6, it appears that “the difference” (line 2) should be “a difference”. It appears that “the voltage” (last line) should be “a voltage”.
Re claim 7, it appears that “a LLC” should be “an LLC”.
Re claim 11, it appears that “the difference” (line 3) should be “a difference”.
Re claim 15, it appears that “the noise” (line 3) should be “a noise”.
Re claim 16, it appears that “the difference” (lines 3-4) should be “a difference”. It appears that “the voltage” (last line) should be “a voltage”.
Re claim 17, it appears that “a LLC” should be “an LLC”.
Re claim 20, it appears that “the difference” (lines 3, 6) should be “a difference”. It appears that “the voltage” (line 7) should be “a voltage”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3 and 12-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Re claim 3, it is unclear what “the first input terminal” (line 10) is referring to. Is it referring to the selecting circuit, the differential detecting circuit, or something else? It is unclear what “the second input terminal” (line 11) is referring to. Is it referring to the selecting circuit, the differential detecting circuit, or something else? For purposes of examination, the first and second input terminals will be of the selecting circuit.
Re claim 12, it is unclear what “the output terminal” (line 7) is referring to. Is it referring to the differential detecting circuit, the voltage dividing circuit, or something else? For purposes on examination, it will be referred to the differential detecting circuit. It is unclear what “the first input terminal” (line 10) is referring to. Is it referring to the selecting circuit, the differential detecting circuit, or something else? It is unclear what “the second input terminal” (line 12) is referring to. Is it referring to the selecting circuit, the differential detecting circuit, or something else? For purposes of examination, the first and second input terminals will be of the selecting circuit. It is unclear what “the output terminal” (line 15) is referring to. Is it referring to the selecting circuit, the differential detecting circuit, the voltage dividing circuit, or something else? For purposes on examination, it will be referred to the selecting circuit.
Claims 13-15 inherit the same from claim 12.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 6, 9, and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Okamoto et al. (“Okamoto”, US 2006/0175984).
Re claim 1, Okamoto teaches a switching converter [Fig 5] comprising: a front stage circuit [Uc] configured to generate a first output voltage [across Cx] between a first node [T21] and a second node [T22]; a voltage dividing circuit [Vx] coupled between the first node [T21] and a third node [Gndx] and configured to generate a first voltage signal [Sv] at an output terminal of the voltage dividing circuit; a current sensing circuit [Ix] coupled between the third node and the second node; a rear stage circuit [Uz, Swt] coupled between the first node and the third node to receive a bus voltage [VL] and configured to convert the bus voltage into a second output voltage [output of Uz]; and a voltage sensing circuit [Ua] coupled to the output terminal of the voltage dividing circuit to receive the first voltage signal and coupled to the third node to receive a second voltage signal [Si], wherein the voltage sensing circuit is configured to generate a voltage sensing signal [Sg] indicative of the first output voltage based on the first voltage signal and the second voltage signal.
Re claim 6, Okamoto teaches wherein the rear stage circuit is configured to sense the bus voltage [VL] based on the difference between the first voltage signal [Sv indicating VL] and the voltage at the third node [Gndx, paragraph 69, Uz operates based on VL].
Re claim 9, Okamoto teaches a switch control circuit [as shown in Fig 6] configured to receive the voltage sensing signal and the second voltage signal and to generate a switch control signal [output of Gx] to control the front stage circuit based on the voltage sensing signal and the second voltage signal.
Re claim 19, Okamoto teaches a control method [Fig 5] for a switching converter with a front stage circuit [Uc] providing a first output voltage [across Cx] between a first node [T21] and a second node [T22], a voltage dividing circuit [Vx] coupled between the first node and a third node [Gndx] and a current sensing circuit [Ix] coupled between the third node and the second node, the control method comprising: receiving a first voltage signal [Sv] from an output terminal of the voltage dividing circuit; receiving a second voltage signal [Si] from the third node; generating a voltage sensing signal [Sg] indicative of the first output voltage based on the first voltage signal and the second voltage signal; and generating a switch control signal [output of Gx] to control the front stage circuit based on the voltage sensing signal and the second voltage signal.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 5, 8, 10, 16, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okamoto in view of Pervaiz (US 11,575,314).
Re claim 4, Okamoto teaches the limitations as applied to the claim above but does not teach wherein the front stage circuit comprises a totem pole PFC (power factor correction) circuit.
Pervaiz teaches a device [Fig 3c] having a front stage circuit comprising a totem pole PFC (power factor correction) circuit [111b]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Okamoto to include the features of Pervaiz because it is used to increase thermal performance which reduces conduction losses, thus improving the utility of the device, which increases efficiency.
Re claim 5, Okamoto teaches the limitations as applied to the claim above but does not teach wherein the second voltage signal represents a current flowing through an inductor of the totem pole PFC circuit.
Pervaiz teaches wherein the second voltage signal represents a current flowing through an inductor of the totem pole PFC circuit. [Col 18, ln 4-9, “The current sense pin (I.sub.D_s, pin 4) is used to sense the falling portion of the inductor current as a voltage across the sense resistor R.sub.Sense, which corresponds to the synchronous rectifier current (sometimes referred to herein as diode current, or I.sub.D) during the synchronous rectifier conduction period, t.sub.SR.”] It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Okamoto to include the features of Pervaiz because it is used to increase thermal performance which reduces conduction losses, thus improving the utility of the device, which increases efficiency.
Re claim 8, Okamoto teaches the limitations as applied to the claim above but does not teach wherein the voltage sensing circuit is integrated in an integrated control circuit, wherein the output terminal of the voltage dividing circuit is coupled to a first pin of the integrated control circuit and the third node is coupled to a second pin of the integrated control circuit.
Pervaiz teaches a device [Fig 3c] wherein the voltage sensing circuit is integrated in an integrated control circuit [105], wherein the output terminal of the voltage dividing circuit is coupled to a first pin of the integrated control circuit [at pin 1] and the third node is coupled to a second pin of the integrated control circuit [at pin 4]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Okamoto to include the features of Pervaiz because it is used to reduce component size with lower power consumption, thus improving the utility of the device, which increases efficiency.
Re claim 10, Okamoto teaches a control circuit [Fig 6] for a switching converter [Fig 5] with a front stage circuit [Uc] providing a first output voltage [VL] between a first node [T21] and a second node [T22], a voltage dividing circuit [Vx] coupled between the first node and a third node [Gndx] and a current sensing circuit [Ix] coupled between the third node and the second node, the control circuit comprising: coupled to an output terminal of the voltage dividing circuit to receive a first voltage signal [Sv]; coupled to the third node to receive a second voltage signal [Si]; provide a switch control signal [output of Gx] to control the front stage circuit; coupled to the second node and coupled to a reference ground of the control circuit [Gndx]; a voltage sensing circuit [Ua] coupled to receive the first voltage signal, coupled to receive the second voltage signal, wherein the voltage sensing circuit is configured to generate a voltage sensing signal [Sg] indicative of the first output voltage based on the first voltage signal and the second voltage signal; and a switch control circuit [Gx] configured to receive the voltage sensing signal and the second voltage signal and to generate the switch control signal based on the voltage sensing signal and the second voltage signal but does not teach a first pin, a second pin, a third pin, and a fourth pin.
Pervaiz teaches an integrated control circuit having a first pin [coupled to Vsense at pin 1], a second pin [coupled to Rsense at pin 4], a third pin [coupled to driver at pins 13, 14], and a fourth pin [coupled to gnd at pin 9]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Okamoto to include the features of Pervaiz because it is used to reduce component size with lower power consumption, thus improving the utility of the device, which increases efficiency.
Re claim 16, Okamoto teaches wherein the switching converter further comprises a rear stage circuit [Uz, Swt] coupled between the first node [T21] and the third node [Gndx] to receive a bus voltage [VL], the rear stage circuit is configured to sense the bus voltage [across Rz] based on the difference between the first voltage signal and the voltage at the third node [paragraph 70].
Re claim 18, Okamoto teaches the limitations as applied to the claim above but does not teach wherein the front stage circuit comprises a totem pole PFC circuit and the second voltage signal represents a current flowing through an inductor of the totem pole PFC circuit.
Pervaiz teaches a device [Fig 3c] having a front stage circuit comprising a totem pole PFC (power factor correction) circuit [111b] and wherein the second voltage signal represents a current flowing through an inductor of the totem pole PFC circuit. [Col 18, ln 4-9, “The current sense pin (I.sub.D_s, pin 4) is used to sense the falling portion of the inductor current as a voltage across the sense resistor R.sub.Sense, which corresponds to the synchronous rectifier current (sometimes referred to herein as diode current, or I.sub.D) during the synchronous rectifier conduction period, t.sub.SR.”] It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Okamoto to include the features of Pervaiz because it is used to increase thermal performance which reduces conduction losses, thus improving the utility of the device, which increases efficiency.
Claim 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okamoto in view of Liu et al. (“Liu”, US 2023/0111992).
Re claim 7, Okamoto teaches the limitations as applied to the claim above but does not teach wherein the rear stage circuit comprises an LLC resonant converting circuit.
Okamoto teaches wherein the rear stage circuit comprises an LLC resonant converting circuit [Multi-mode LLC]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Okamoto to include the features of Liu because it is used to lower switching losses and EMI, thus improving the utility of the device, which increases efficiency.
Claim 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okamoto in view of Pervaiz and Liu.
Re claim 17, Okamoto teaches the limitations as applied to the claim above but does not teach wherein the rear stage circuit comprises an LLC resonant converting circuit.
Okamoto teaches wherein the rear stage circuit comprises an LLC resonant converting circuit [Multi-mode LLC]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Okamoto to include the features of Liu because it is used to lower switching losses and EMI, thus improving the utility of the device, which increases efficiency.
Allowable Subject Matter
Claims 2, 11, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 3 and 12-15 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art fails to teach or disclose:
Re claim 2 and its dependents thereof, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “when the front stage circuit performs power operation, the voltage sensing circuit is configured to generate the voltage sensing signal based on the difference between the first voltage signal and the second voltage signal; and when the front stage circuit stops power operation, the voltage sensing circuit is configured to generate the voltage sensing signal based on the difference between the first voltage signal and the voltage at the second node” in combination with the additionally claimed features, as are claimed by Applicant.
Re claim 11 and its dependents thereof, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “when the front stage circuit performs power operation, the voltage sensing circuit is configured to generate the voltage sensing signal based on the difference between the first voltage signal and the second voltage signal; and when the front stage circuit stops power operation, the voltage sensing circuit is configured to generate the voltage sensing signal based on the first voltage signal” in combination with the additionally claimed features, as are claimed by Applicant.
Re claim 20 and its dependents thereof, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “generating the voltage sensing signal based on the difference between the first voltage signal and the second voltage signal when the front stage circuit performs power operation; and generating the voltage sensing signal based on the difference between the first voltage signal and the voltage at the second node when the front stage circuit stops power operation” in combination with the additionally claimed features, as are claimed by Applicant.
Conclusion
Examiner's Note:
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAKAISHA JACKSON whose telephone number is (571)270-3111. The examiner can normally be reached on M-F 8:00-5:00.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MONICA LEWIS can be reached on 571-272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LaKaisha Jackson/
Examiner, Art Unit 2838