DETAILED ACTION
This office action is in response to the amendment filed 05/26/2026.
Drawings
The drawings were received on 05/26/2026. These drawings are acceptable.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 6, 9, and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Okamoto et al. (“Okamoto”, US 2006/0175984).
Re claim 1, Okamoto teaches a switching converter [Fig 5] comprising: a front stage circuit [Uc] configured to generate a first output voltage [across Cx] between a first node [T21] and a second node [T22]; a voltage dividing circuit [Vx] coupled between the first node [T21] and a third node [Gndx] and configured to divide a bus voltage [VL]; a current sensing circuit [Ix] coupled between the third node and the second node; a rear stage circuit [Uz, Swt] coupled between the first node and the third node to receive the bus voltage [VL] and configured to convert the bus voltage into a second output voltage [output of Uz]; and a voltage sensing circuit [Ua] coupled to an output terminal of the voltage dividing circuit to receive a first voltage signal [Sv] and coupled to the third node to receive a second voltage signal [Si], wherein the voltage sensing circuit is configured to generate a voltage sensing signal [Sg] indicative of the first output voltage based on the first voltage signal and the second voltage signal.
Re claim 6, Okamoto teaches wherein the rear stage circuit is configured to sense the bus voltage [VL] based on a difference between the first voltage signal [Sv indicating VL] and a voltage at the third node [Gndx, paragraph 69, Uz operates based on VL].
Re claim 9, Okamoto teaches a switch control circuit [as shown in Fig 6] configured to receive the voltage sensing signal and the second voltage signal and to generate a switch control signal [output of Gx] to control the front stage circuit based on the voltage sensing signal and the second voltage signal.
Re claim 19, Okamoto teaches a control method [Fig 5] for a switching converter with a front stage circuit [Uc] providing a first output voltage [across Cx] between a first node [T21] and a second node [T22], the control method comprising: receiving a first voltage signal [Sv] from an output terminal of a voltage dividing circuit [Vx] coupled between the first node and a third node [T12] and configured to divide a bus voltage [VL]; receiving a second voltage signal [Si] from the third node; generating a voltage sensing signal [Sg] indicative of the first output voltage based on the first voltage signal and the second voltage signal; and generating a switch control signal [output of Gx] to control the front stage circuit based on the voltage sensing signal and the second voltage signal.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 5, 8, 10, 16, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okamoto in view of Pervaiz (US 11,575,314).
Re claim 4, Okamoto teaches the limitations as applied to the claim above but does not teach wherein the front stage circuit comprises a totem pole PFC (power factor correction) circuit.
Pervaiz teaches a device [Fig 3c] having a front stage circuit comprising a totem pole PFC (power factor correction) circuit [111b]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Okamoto to include the features of Pervaiz because it is used to increase thermal performance which reduces conduction losses, thus improving the utility of the device, which increases efficiency.
Re claim 5, Okamoto teaches the limitations as applied to the claim above but does not teach wherein the second voltage signal represents a current flowing through an inductor of the totem pole PFC circuit.
Pervaiz teaches wherein the second voltage signal represents a current flowing through an inductor of the totem pole PFC circuit. [Col 18, ln 4-9, “The current sense pin (I.sub.D_s, pin 4) is used to sense the falling portion of the inductor current as a voltage across the sense resistor R.sub.Sense, which corresponds to the synchronous rectifier current (sometimes referred to herein as diode current, or I.sub.D) during the synchronous rectifier conduction period, t.sub.SR.”] It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Okamoto to include the features of Pervaiz because it is used to increase thermal performance which reduces conduction losses, thus improving the utility of the device, which increases efficiency.
Re claim 8, Okamoto teaches the limitations as applied to the claim above but does not teach wherein the voltage sensing circuit is integrated in an integrated control circuit, wherein the output terminal of the voltage dividing circuit is coupled to a first pin of the integrated control circuit and the third node is coupled to a second pin of the integrated control circuit.
Pervaiz teaches a device [Fig 3c] wherein the voltage sensing circuit is integrated in an integrated control circuit [105], wherein the output terminal of the voltage dividing circuit is coupled to a first pin of the integrated control circuit [at pin 1] and the third node is coupled to a second pin of the integrated control circuit [at pin 4]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Okamoto to include the features of Pervaiz because it is used to reduce component size with lower power consumption, thus improving the utility of the device, which increases efficiency.
Re claim 10, Okamoto teaches a control circuit [Fig 6] for a switching converter [Fig 5] with a front stage circuit [Uc] providing a first output voltage [VL] between a first node [T21] and a second node [T22], the control circuit comprising: coupled to an output terminal of a voltage dividing circuit [Vx] coupled between the first node and a third node [T12] and configured to divide a bus voltage [VL], configured to receive a first voltage signal [Sv]; coupled to the third node to receive a second voltage signal [Si]; provide a switch control signal [output of Gx] to control the front stage circuit; coupled to the second node and coupled to a reference ground of the control circuit [Gndx]; a voltage sensing circuit [Ua] coupled to receive the first voltage signal, coupled to receive the second voltage signal, wherein the voltage sensing circuit is configured to generate a voltage sensing signal [Sg] indicative of the first output voltage based on the first voltage signal and the second voltage signal; and a switch control circuit [Gx] configured to receive the voltage sensing signal and the second voltage signal and to generate the switch control signal based on the voltage sensing signal and the second voltage signal but does not teach a first pin, a second pin, a third pin, and a fourth pin.
Pervaiz teaches an integrated control circuit having a first pin [coupled to Vsense at pin 1], a second pin [coupled to Rsense at pin 4], a third pin [coupled to driver at pins 13, 14], and a fourth pin [coupled to gnd at pin 9]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Okamoto to include the features of Pervaiz because it is used to reduce component size with lower power consumption, thus improving the utility of the device, which increases efficiency.
Re claim 16, Okamoto teaches wherein the switching converter further comprises a rear stage circuit [Uz, Swt] coupled between the first node [T21] and the third node [Gndx] to receive the bus voltage [VL], the rear stage circuit is configured to sense the bus voltage [across Rz] based on a difference between the first voltage signal and a voltage at the third node [paragraph 70].
Re claim 18, Okamoto teaches the limitations as applied to the claim above but does not teach wherein the front stage circuit comprises a totem pole PFC circuit and the second voltage signal represents a current flowing through an inductor of the totem pole PFC circuit.
Pervaiz teaches a device [Fig 3c] having a front stage circuit comprising a totem pole PFC (power factor correction) circuit [111b] and wherein the second voltage signal represents a current flowing through an inductor of the totem pole PFC circuit. [Col 18, ln 4-9, “The current sense pin (I.sub.D_s, pin 4) is used to sense the falling portion of the inductor current as a voltage across the sense resistor R.sub.Sense, which corresponds to the synchronous rectifier current (sometimes referred to herein as diode current, or I.sub.D) during the synchronous rectifier conduction period, t.sub.SR.”] It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Okamoto to include the features of Pervaiz because it is used to increase thermal performance which reduces conduction losses, thus improving the utility of the device, which increases efficiency.
Claim 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okamoto in view of Liu et al. (“Liu”, US 2023/0111992).
Re claim 7, Okamoto teaches the limitations as applied to the claim above but does not teach wherein the rear stage circuit comprises an LLC resonant converting circuit.
Okamoto teaches wherein the rear stage circuit comprises an LLC resonant converting circuit [Multi-mode LLC]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Okamoto to include the features of Liu because it is used to lower switching losses and EMI, thus improving the utility of the device, which increases efficiency.
Claim 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okamoto in view of Pervaiz and Liu.
Re claim 17, Okamoto teaches the limitations as applied to the claim above but does not teach wherein the rear stage circuit comprises an LLC resonant converting circuit.
Okamoto teaches wherein the rear stage circuit comprises an LLC resonant converting circuit [Multi-mode LLC]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Okamoto to include the features of Liu because it is used to lower switching losses and EMI, thus improving the utility of the device, which increases efficiency.
Allowable Subject Matter
Claims 2, 3, 11-15, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: please see the office action dated 02/26/2026 for reasons for allowable subject matters.
Response to Arguments
Applicant's arguments filed 05/26/2026 have been fully considered but they are not persuasive.
Applicant argues “it is respectfully submitted that the output voltage detecting unit Vx cannot be read as the voltage dividing circuit of claim 1. Specifically, we can see from FIG. 5 that the output voltage detecting unit Vx is coupled between the terminal T21 and the ground Gndx and is configured to divide the voltage across Cx (which is read as the first output voltage in the present Office Action), rather than being configured to divide the voltage VL (which is read as the bus voltage in the present Office Action). It is obviously different from "a voltage dividing circuit ... configured to divide a bus voltage". Thus, the output voltage detecting unit Vx cannot be read as the voltage dividing circuit of claim 1.”
The Examiner respectfully disagrees. Paragraph 45 of Okamoto clearly teaches that the output voltage detecting unit Vx is configured to divide the bus voltage VL. Specifically, it recites “In general, an output voltage detecting unit Vx detects an output voltage VL of the power supply circuit Ux, that is, a lamp voltage, to generate an output voltage detecting signal Sv and outputs the generated signal to the power supply control circuit Ua”. Further, paragraph 71 recites “the output voltage detecting unit Vx can be formed of a resistor divider”. Therefore, Okamoto teaches the claimed limitation, and rejection is proper.
Applicant further argues “the power supply control circuit Ua cannot be read as the voltage sensing circuit and the gate driving signal Sg cannot be read as the voltage sensing signal indicative of the first output voltage. Specifically, as discussed in paragraph [0069] of Okamoto (which is reproduced below), the gate driving signal Sg is a control signal used for controlling the turning-on and turning-off of the switching element Qx. rather than a signal indicative of the output voltage. …. Thus, Okamoto is obviously different form "the voltage sensing circuit is configured to generate a voltage sensing signal indicative of the first output voltage based on the first voltage signal and the second voltage signal" of claim 1”.
The Examiner respectfully disagrees. Okamoto teaches in paragraph 45 that “…the power supply control circuit Ua determines a lamp current target value for realizing target power according to the level of the output voltage detecting signal Sv, and perform feedback control to adjust the capability of the converter Uc in order to realize the target value, on the basis of a gate driving signal Sg”. Meaning, the signal Sg is determined based on the how the sensed voltage Sv relates to the target voltage, as determined by the power supply control circuit Ua. Therefore rejection is proper.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAKAISHA JACKSON whose telephone number is (571)270-3111. The examiner can normally be reached on M-F 8:00-5:00.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MONICA LEWIS can be reached on 571-272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LaKaisha Jackson/
Primary Examiner, Art Unit 2838
Prosecution Insights