DETAILED ACTION
Claims 1-21 are pending. Claims 1, 10, 18, and 21 are in independent form.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 2 is objected to because of the following informalities: “at least one routing processor configured in a manner to device the target device and parity device for each memory address”. The verb device in this sentence does not make sense. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the redundant array of independent devices (RAID)" in line 3. There is insufficient antecedent basis for this limitation in the claim.
Claim 2 recites the limitation "the switch" in line 16. There is insufficient antecedent basis for this limitation in the claim.
Claim 3 recites the limitation “the component failures” in line 1. There is insufficient antecedent basis for this limitation in the claim.
Claim 7 recites the limitation “the parity” in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim 10 recites the limitation “the parity group” in line 19. There is insufficient antecedent basis for this limitation in the claim.
Claim 10 recites the limitation “the parity group update” in line 20. There is insufficient antecedent basis for this limitation in the claim.
Claim 10 recites the limitation “the fault tolerant engine” in line 6. There is insufficient antecedent basis for this limitation in the claim.
Claim 11 recites the limitation “the component failures” in line 1. There is insufficient antecedent basis for this limitation in the claim.
Claim 15 recites the limitation “the parity” in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim 18 recites the limitation “the parity group” in line 20. There is insufficient antecedent basis for this limitation in the claim.
Claim 18 recites the limitation “the parity group update” in line 21. There is insufficient antecedent basis for this limitation in the claim.
Claim 19 recites the limitation “the component failures” in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claims 3-9, 11-17, and 19-20 are dependent upon rejected parent claims. Therefore, claims 3-9, 11-17, and 19-20 inherit the rejections from there parent claims through the virtue of dependency.
Claim Rejections - 35 USC § 103
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Publication No. 2006/0075283 to Hartung et al. (“Hartung”) in view of U.S. Publication No. 2018/0060367 to Ioannou et al. ("Ioannou") in view of U.S. Publication No. 2024/0427526 to Del Gatto et al. (“Del Gatto”) and further in view of U.S. Publication No. 2017/0031759 to Galbraith et al. (“Galbraith”).
Regarding claim 1, Hartung teaches:
A system configured for connecting to a host (Hartung: Paragraph [0029], “One or more data processing systems 102 are connected to a storage system 104. Data-processing systems 102 can be in the form of computer servers, stand-alone desktop computers, PCs, workstations and the like”; Paragraph [0030], “A storage controller interface 202 receives data from data processing system 102. Examples of storage controller interface 202 include Fibre Channel Interface, SCSI host adapter, SATA Interface, and iSCSI host adapter. Storage controller interface 202 is used to connect one or more data processing systems 102 to storage system 104”), comprising:
a memory protocol unit (MPU) configured for connecting one of at least two switch paths within the redundant array of independent devices (RAID) fabric to the host (Hartung: Fig. 2, # 208, 210a, 210b, 210c; wherein there are three paths indicated by arrows from the 208 to the command switches; Paragraph [0030], “Disk data/command controller 208 is connected to a plurality of data/command switches 210 a, 210 b, and 210 c. Disk data/command controller 208 sends data/commands to the data/command switch corresponding to the disk drive to which data/commands have to be routed”; wherein 208 is interpreted as the MPU); and
a RAID fabric including two or more leaf switches (Hartung: Fig. 2, # 208, 210a, 210b, 210c; Paragraph [0030], “Disk data/command controller 208 is connected to a plurality of data/command switches 210 a, 210 b, and 210 c. Disk data/command controller 208 sends data/commands to the data/command switch corresponding to the disk drive to which data/commands have to be routed”; wherein the leaf switches are the command switches acting as leaf switches at the reception of data to the storage disk drives);
However, Hartung does not appear to teach:
a routing processor coupled to the MPU along a respective one of the two switch paths;
a cluster of fault tolerant engines coupled to the routing processor;
each device (i) coupled to a corresponding one of the fault tolerant engines.
However, in the same field of endeavor, Ioannou teaches:
a routing processor coupled to the MPU along a respective one of the two switch paths (Ioannoi: Fig. 1A and Fig. 1B, #122, #112; wherein the interface node is equivalent to the leaf switch, inside the interface node there is a host side switching fabric which is equivalent to the routing processor and is coupled to the processor system 102; Paragraph [0027], “connect to a host side switching fabric 112, which can be implemented, for example, by a Peripheral Component Interconnect express (PCIe) switch or other suitable switch. Host side switching fabric 112 transfers data between interface cards 111 and one or more processors within interface node 122”; wherein the interface node is the leaf switch, and the host side switching fabric is the routing processor which handles routing to the processor);
a cluster of fault tolerant engines coupled to the routing processor (Ioannoi: Paragraph [0033], “Controller 113 also includes a deduplication engine 125 that executes the search for duplicates upon incoming writes or during background deduplication. When a duplicate is found, the deduplication engine 125 uses the address mapping engine 116 to update address mapping data structures 158 and reference counters 156 including the potentially cached copies in the address mapping cache 121 and the reference counter cache 117. When the new write IO is not a duplicate, deduplication engine 125 inserts the fingerprint generated by the fingerprint engine 114 into the fingerprint index 154 directly and/or into the fingerprint index cache 119”; wherein the controller 113 is interpreted as the fault tolerant engines which includes deduplication engine 125 that handles some fault tolerance like duplicate signals; and wherein the controller 113 is inside the interface node 122 which is interpreted as the leaf switch);
each device (i) coupled to a corresponding one of the fault tolerant engines (Ioannoi: Fig. 1A, #124 and #122; wherein the RAID controller is coupled to the interface node and can by the transitive property is coupled to the fault tolerant engine which is the deduplication engine; Paragraph [0026], “Each interface node 122 is coupled to each of multiple Redundant Array of Inexpensive Disks (RAID) controllers 124 in order to facilitate fault tolerance and load balancing”; wherein the Raid Controller is the interpreted as the devices; Paragraph [0027], “Controller 113 is additionally coupled to RAID controllers 124 through storage side switching fabric 123, which can be implemented with a PCIe switch or other switch technology”; wherein the raid controller uses PCIe)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method taught by Hartung by having a leaf switch comprising a routing processor and fault tolerant engines connected to devices, as taught by Ioannou. One of ordinary skill in the art would have been motivated to use the methods of Ioannou because it will improve performance of the system and reduce wear on drives. (Ioannou: Paragraphs [0005]-[0006]).
However, the Hartung/Ioannou combination does not appear to teach:
a cluster of fabric fault tolerant CXL devices.
However, in the same field of endeavor, Del Gatto teaches:
a cluster of fabric fault tolerant CXL devices (Del Gatto: Paragraph [0012], “CXL is a high-speed central processing unit (CPU)-to-device and CPU-to-memory interconnect designed to accelerate next-generation data center performance. CXL technology maintains memory coherency between the CPU memory space and memory on attached devices, which allows resource sharing for higher performance, reduced software stack complexity, and lower overall system cost. CXL is designed to be an industry open standard interface for high-speed communications, as accelerators are increasingly used to complement CPUs in support of emerging applications such as artificial intelligence and machine learning. CXL technology is built on the PCIe infrastructure, leveraging PCIe physical and electrical interfaces to provide advanced protocol in areas such as input/output (I/O) protocol, memory protocol (e.g., initially allowing a host to share memory with an accelerator), and coherency interface”; wherein CXL can be built on PCIe infrastructure therefore can be combined with the RAID controller in Ioannoi for the same benefits),
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method taught by the Hartung/Ioannou combination by having the devices as CXL devices, as taught by Del Gatto. One of ordinary skill in the art would have been motivated to use the methods of Del Gatto because it will improve coherency and performance. (Del Gatto: Paragraph [0012]).
However, the Hartung/Ioannou/Del Gatto combination does not appear to teach:
(ii) including a lock controller;
wherein the lock controller is configured to limit modifications to a parity group in the cluster of fabric fault tolerant CXL devices created via write requests and occurring during a single instance in time.
However, in the same field of endeavor, Galbraith teaches:
(ii) including a lock controller (Galbraith: Paragraph [0019], “To manage data transfers between the compute device 105 and the storage drives 120, the RAID adapter 110 includes a PSL engine 115 which grants the parity stripe locks mentioned above”; wherein the RAID adapter can be interpreted as the RAID controller in Ioannoi; wherein the lock controller is the PSL engine 115);
wherein the lock controller is configured to limit modifications to a parity group in the cluster of fabric fault tolerant CXL devices created via write requests and occurring during a single instance in time (Galbraith: Paragraph [0019], “To manage data transfers between the compute device 105 and the storage drives 120, the RAID adapter 110 includes a PSL engine 115 which grants the parity stripe locks mentioned above”; Paragraph [0019], “Because it is possible for two requests from the computing devices 105 to write data to different locations within a stripe at the same time, the simultaneous writes may incorrectly update the parity data stored in parity drive 120P. The locks prevent this from occurring”; wherein the lock limits writes to the stripe which based on the present specification can be interpreted as a parity group; furthermore, the lock is to prevent simultaneous writes which reads on write request occurring during a single instance in time).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method taught by the Hartung/Ioannou/Del Gatto combination by having a lock controller that limits modifications at the same time to prevent corruption, as taught by Galbraith. One of ordinary skill in the art would have been motivated to use the methods of Galbraith because it will prevent incorrectly updating parity data from simultaneous writes. (Galbraith: Paragraph [0019]).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Hartung and further in view of Galbraith.
Regarding claim 21, Hartung teaches:
A system configured for connecting to a host (Hartung: Paragraph [0029], “One or more data processing systems 102 are connected to a storage system 104. Data-processing systems 102 can be in the form of computer servers, stand-alone desktop computers, PCs, workstations and the like”; Paragraph [0030], “A storage controller interface 202 receives data from data processing system 102. Examples of storage controller interface 202 include Fibre Channel Interface, SCSI host adapter, SATA Interface, and iSCSI host adapter. Storage controller interface 202 is used to connect one or more data processing systems 102 to storage system 104”).
two or more fabric switches coupled, via a plurality of first switch links, to the cluster, wherein each fabric switch (Hartung: Fig. 2, # 208, 210a, 210b, 210c; wherein there are three paths indicated by arrows from the 208 to the command switches; wherein the links are the paths; Paragraph [0030], “Disk data/command controller 208 is connected to a plurality of data/command switches 210 a, 210 b, and 210 c. Disk data/command controller 208 sends data/commands to the data/command switch corresponding to the disk drive to which data/commands have to be routed”) comprises:
a leaf switch (Hartung: Fig. 2, # 208, 210a, 210b, 210c; Paragraph [0030], “Disk data/command controller 208 is connected to a plurality of data/command switches 210 a, 210 b, and 210 c. Disk data/command controller 208 sends data/commands to the data/command switch corresponding to the disk drive to which data/commands have to be routed”; wherein the leaf switches are the command switches acting as leaf switches at the reception of data to the storage disk drives).
However, Hartung does not appear to explicitly teach:
a plurality of fabric fault tolerant memory devices in a cluster, wherein for a given destination address one of the devices is a target device and another one of the devices is a parity device; and
at least one fault tolerant engine coupled to a corresponding one of the devices of the cluster, the at least one fault tolerant engine configured to perform memory operations including an access operation;
wherein, when the access operation is a write access, the at least one fault tolerant engine performs at least one of (i) locks the parity device, (ii) preserves old data written to the parity device, (iii) writes new data to the target device, and (iv) unlocks the parity device.
However, in the same field of endeavor, Galbraith teaches:
a plurality of fabric fault tolerant memory devices in a cluster, wherein for a given destination address one of the devices is a target device and another one of the devices is a parity device (Galbraith: Paragraph [0018], “Thus, when performing a write operation, the RAID adapter 110 may store a portion in A1 on driver 120A and another portion on drive 120B. This enables simultaneously reads where the data in the same stripe can be read from two drives 120 (i.e., drives 120A and 120B) in parallel. Moreover, to increase data redundancy, the system 100 includes the parity drive 120P which stores parity data for each of the stripes”); and
at least one fault tolerant engine coupled to a corresponding one of the devices of the cluster, the at least one fault tolerant engine configured to perform memory operations including an access operation (Galbraith: Paragraph [0019], “To manage data transfers between the compute device 105 and the storage drives 120, the RAID adapter 110 includes a PSL engine 115 which grants the parity stripe locks mentioned above”; Paragraph [0019], “Because it is possible for two requests from the computing devices 105 to write data to different locations within a stripe at the same time, the simultaneous writes may incorrectly update the parity data stored in parity drive 120P. The locks prevent this from occurring”; wherein the access operation is the writing of data to a location after the lock is completed);
wherein, when the access operation is a write access, the at least one fault tolerant engine performs at least one of (i) locks the parity device (Galbraith: Paragraph [0019], “To manage data transfers between the compute device 105 and the storage drives 120, the RAID adapter 110 includes a PSL engine 115 which grants the parity stripe locks mentioned above”; Paragraph [0019], “Because it is possible for two requests from the computing devices 105 to write data to different locations within a stripe at the same time, the simultaneous writes may incorrectly update the parity data stored in parity drive 120P. The locks prevent this from occurring”; wherein the lock limits writes to the stripe which based on the present specification can be interpreted as a parity group; furthermore, the lock is to prevent simultaneous writes which reads on write request occurring during a single instance in time), (ii) preserves old data written to the parity device, (iii) writes new data to the target device, and (iv) unlocks the parity device.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method taught by Hartung by having a lock controller that limits modifications at the same time to prevent corruption and to have devices where an address points to a parity device and a target device, as taught by Galbraith. One of ordinary skill in the art would have been motivated to use the methods of Galbraith because it will prevent incorrectly updating parity data from simultaneous writes. (Galbraith: Paragraph [0019]).
Allowable Subject Matter
Claims 2-20 are rejected under non-art rejections, but would be allowable if rewritten to overcome the non-art rejections.
The following is a statement of reasons for the indication of allowable subject matter:
As to claim 2, it contains allowable subject matter when the claim is taken as a whole. See the bolded/italicized/underlined text indicating aspects that in combination with the remainder of the claim differentiate it from prior art:
A system configured for connecting to a host, the system comprising:
a plurality of fabric fault tolerant memory devices in a cluster, wherein for a given destination address one of the devices is a target device and another one of the devices is a parity device; and
two or more fabric switches coupled, via a plurality of first switch links, to the cluster, wherein each fabric switch comprises:
a leaf switch comprising:
at least one fault tolerant engine coupled to a corresponding one of the devices of the cluster, the at least one fault tolerant engine configured to perform memory operations including an access operation;
wherein, when the access operation is a write access, the at least one fault tolerant engine performs at least one of (i) locks the parity device, (ii) preserves old data written to the parity device, (iii) writes new data to the target device, and (iv) unlocks the parity device;
at least one routing processor configured in a manner to device the target device and parity device for each memory address, enabling the switch to determine the port of the target device and the port of the parity device;
a memory protocol unit (MPU) coupled, via a plurality of second switch links, to the two or more fabric switches and the host, the MPU being configured to:
store a record of requests by the host that are active in the two or more fabric switches;
select one of the fabric switches to transfer the requests to the target device based on a target address and a current state of the two or more fabric switches, wherein the current state is an active state or a failed state; and
issue the request to the target device using the selected fabric switch; and
a lock controller within one or more of the fabric fault tolerant memory devices configured to preserve old write data for active parity group updates;
wherein the preserving ensures the lock controller retains data for keeping the parity group in a consistent state when one of the fabric switches fails during a parity group update.
As to claim 10, it contains allowable subject matter when the claim is taken as a whole. See the bolded/italicized/underlined text indicating aspects that in combination with the remainder of the claim differentiate it from prior art:
A method comprising:
connecting two or more fabric switches to at least one group of devices in a cluster and at least one host, wherein the at least one group of devices includes at least a target data device, other data devices, and a parity device;
performing an access operation using at least one redundant array of independent CXL devices (RAID) engine coupled to the cluster, wherein the fault tolerant engine is provided in a leaf switch within each fabric switch; and
determining a path for a request received from the at least one host to the target data device using at least one routing processor coupled to the fault tolerant engine, wherein the routing processor is provided in the leaf switch;
storing a record of all requests by the at least one host that are active in the two or more fabric switches;
selecting one of the fabric switches to transfer the request to the target device based on a target address and a current state of the two or more fabric switches, wherein the current state of each fabric switch being one of a plurality of states including an active state and a failed state;
issuing the request to the target device using the selected fabric switch; and
preserving old write data for all active parity group updates to retain data necessary to keep the parity group in a consistent state when one of the fabric switches fails during the parity group update.
As to claim 18, it contains allowable subject matter when the claim is taken as a whole. See the bolded/italicized/underlined text indicating aspects that in combination with the remainder of the claim differentiate it from prior art:
A non-transitory computer readable storage medium storing instructions, which when executed, cause a processing device to:
connect two or more fabric switches to at least one group of devices in a cluster and at least one host, wherein the at least one group of devices includes at least a target data device, other data devices, and a parity device;
perform an access operation using at least one redundant array of independent CXL devices (RAID) controller coupled to the cluster, wherein the fault tolerant engine is provided in a leaf switch within each fabric switch; and
determine a path for a request received from the at least one host to the target data device using at least one routing processor coupled to the fault tolerant engine, wherein the routing processor is provided in the leaf switch;
store a record of all requests by the at least one host that are active in the two or more fabric switches;
select one of the fabric switches to transfer the request to the target device based on a target address and a current state of the two or more fabric switches, wherein the current state of each fabric switch being one of a plurality of states including an active state and a failed state;
issue the request to the target device using the selected fabric switch; and
preserve old write data for all active parity group updates to retain data necessary to keep the parity group in a consistent state when one of the fabric switches fails during the parity group update.
Claims 3-9, 11-17 and 19-20 are respectively dependent upon independent claims 2, 10, and 18. Therefore, claims 3-9, 11-17 and 19-20 contain allowable subject matter by the virtue of dependency.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. (US 20250267065 A1, US 20250036491 A1, US 20220345369 A1, US 10409527 B1, US 20130282980 A1, US 20060041789 A1, US 20040193737 A1, US 20020087751 A1, US 6401170 B1).
US 20250267065 A1: In some examples, one or more aspects of HPC systems (e.g., HPC networking) may be based on peripheral component interconnect express (PCIe). PCIe is a high-speed interface standard that allows for the connection of various internal components in a computer system. PCIe is commonly found in desktop and mobile computers, server systems, set-top boxes, and gaming consoles. PCIe is used for connecting expansion cards (graphics cards, network cards, storage controllers) to a motherboard. In its simplest form, PCIe is a point-to-point connection between two PCIe compatible devices (e.g., between a motherboard and an expansion card or storage device, etc.). PCIe may be used to connect high-speed input output (HSIO) components such as graphics cards, SSDs, capture cards, wireless cards, redundant array of independent disks (RAID) cards, WiFi cards, etc. Compute express link (CXL) is an open standard for high-speed communication between a central processing unit (CPU) and other devices. CXL is built on the PCIe physical and electrical interface.
US 20250036491 A1: In this example, an abstracted system topology is provided that can be used for both CXL-based scale-out and scale out devices. For example, different types of servers are interconnected via a Scaling/Resource Enclosure (SRE) into a single cache coherent server of up to 64 sockets. Multiple switches in the SRE are used to provide fabric fault tolerance and the required bandwidths. CXL memory within the SRE can also be assigned to the server as cache coherent fabric attached memory (FAM) to expand memory independently from central processing units (CPUs). The ASICs 122A, 122B, 124A, 124B within the SRE communicate with each other via switch to provide memory Redundant Array of Independent Disks (RAID) across groups of CXL memory modules. This same topology with CXL from the CPUs to 122A, 122B, 124A, 124B provides a large, scale-out system consisting of CPUs, GPUs, FAM, and other devices. CXL 3.0 is defining Port Based Routing packet formats that will support 4096 total fabric endpoints. To reach this scale, SREs can be interconnected via SS+ links using fabric topologies such as Dragonfly™ or HyperX™ to provide systems with thousands of CPUs, GPUs, and FAM modules with high throughput and extremely low latencies. The proven interconnect fabric technology dynamically detects fabric congestion and routes traffic across all accessible paths to maximize fabric throughput under heavy load.
US 20220345369 A1: When the data is stored in a redundant fashion—in a mirrored or RAID-type array—it can be self-healed automatically and without any administrator intervention. Since data corruption is logged, ZFS can bring to light defects in memory modules (or other hardware) that cause data to be stored on hard drives incorrectly. Scrubbing is given low I/O priority so that it has a minimal effect on system performance and can operate while the storage pool is in use. An advantage of copy-on-write is that, when ZFS writes new data, the blocks containing the old data can be retained, allowing a snapshot version of the file system to be maintained. ZFS snapshots are created very quickly, since all the data composing the snapshot is already stored. They are also space efficient, since any unchanged data is shared among the file system and its snapshots. Initially, snapshots consume no additional disk space within the pool. As data within the active dataset changes, the snapshot consumes disk space by continuing to reference the old data. As a result, the snapshot prevents the data from being freed back to the pool. ZFS also allows writeable snapshots (“clones”) to be created, resulting in two independent file systems that share a set of blocks. As changes are made to any of the clone file systems, new data blocks are created to reflect those changes, but any unchanged blocks continue to be shared, no matter how many clones exist. This is possible due to the copy-on-write design. Snapshots of ZFS file systems and volumes can be sent to remote hosts over the network. This data stream can be an entire file system or volume, or it can be the changes since it was last sent. When sending only the changes, the stream size depends on the number of blocks changed between the snapshots. This provides a very efficient strategy for synchronizing backups.
US 10409527 B1: Likewise, as illustrated in FIG. 4, RAID 5/6 may be deployed as a data protection scheme between a plurality of production disks 410, 430, 460, 470. Accordingly, abstraction of disk RAID 5/6 protection from the physical characteristics of the protected storage may be provided by decoupling allocated resources for RAID 5/6 data protection (e.g., production disks 410, 430, 460, 470) from the physical characteristics of the protected storage of production resources. Protection storage (e.g., virtual pool 2 450) (i.e., storing parity data 490) then may be provided to protect production storage (e.g., virtual pool 1 440) (i.e., storing data 480). In order to provide isolation of the production data, the IO patterns of traditional RAID may require modification to prevent read/write IOs from the parity drives. Accordingly, parity data may be stored to a separate virtual pool. For example, production data may be stored to higher-performant disks with parity data being written to lower-performant disks. It should be understood that cache also may be used in this example embodiment to increase the performance of parity IOs.
US 20130282980 A1: FIG. 9 shows a memory system complex 300 having a plurality of memory systems 200, communicating with a plurality of RAID controllers 10 through a switch fabric 20. The RAID controllers 10 may communicate with the external environment through a network or switch fabric 25 having a plurality of external interfaces 50. Such configurations may provide for redundant communication paths between redundant storage or computational resources, so as to improve response time and provide continuity of service during failure conditions.
US 20060041789 A1: Processes and methods, typically executable on the controller 106, operate to respond to a write operation to one of the first 102A and second 102B data disks by reading old data from the disk that is not written and saving the old data on the meta-file directory and buffer disk 210 in combination with the write operation data. The process copies the old data to a tape drive of the first 214A and second 214B journaling tape drives, while retaining the new data in the meta-directory along with a time stamp. The process can access the storage devices 102A and 102B with the granularity of a per-disk-driver-write that designates only logical unit number (LUN), track, sector, and length, to the particular RAID-1 spindle that is written, reads old data from the other spindle for transfer to the directory and buffer device 210 and consequently to the tape drives 214A and 214B.
US 20040193737 A1: Any one or more of these hosts or storage controllers could also be a RAID controller. Diamond 92 of FIG. 6 determines whether or not a condition or conditions of another host or controller (could be an active host or active controller) has occurred. The detected or determined conditions could include a failure, a hung state, or some other condition of the other host or controller. If the condition is not determined/detected in diamond 92, diamond 92 continues to determine whether or not the conditions have occurred. If diamond 92 determines that a condition or conditions have occurred box 94 sends a signal to a switch (switch could be a storage switch and/or a storage fail-over device or some other logic, functionality or connection) to decouple the other host or controller from a storage device and/or to couple the host or controller (could be an inactive host or inactive controller) to the storage device. The signal sent in box 94 could be a unique signal, a unique sequence of signals or unique combination of signals. Flow can then end or be returned to the input of diamond 92.
US 20020087751 A1: The switch 22 in the storage controller 26 functions to route command, status and data information between two or more circuit elements. In one embodiment, the switch may have sufficient number of ports to allow two hosts to simultaneously access the switch for pertinent data transfer operations involving the storage device. One such implementation of such a multi-ported switch 221 is illustrated in FIG. 5. The switch 22 may be configured to send data to multiple places at the same time. This replication "on the fly" saves in latency and reduces bandwidth requirements. For example, typical multiple destinations during a data write operation may include the cache memory 341, the cache mirror 342, and the parity calculator 321 in the embodiment of FIG. 5.
US 6401170 B1: The RAID system disclosed here uses arbitrated fiber channels or switch fabric to connect multiple host computers and storage array controllers (SAC). Each SAC is designated a primary SAC for an array of storage units, which it normally serves as controller, and as a secondary SAC for another array of storage units. A primary SAC, secondary SAC, and array of storage units is termed a storage unit set. When the primary SAC or associated host computer fails, the failure is detected by an interface chip, which causes the secondary SAC to assume the identify of the primary controller. Using system configuration information from the DASDs, the secondary SAC then controls the storage units of the storage unit set along with the storage units of which it is primary SAC. With this configuration, there is no need for switch apparatus between the storage arrays and there is no interference because dual ported storage units are used.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Matthew N Putaraksa whose telephone number is (303)297-4365. The examiner can normally be reached on Monday-Thursday 7:00am-5:00pm MT.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ashish Thomas can be reached on (571) 272-0631. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair-my.uspto.gov/pair/PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MATTHEW N PUTARAKSA/Examiner, Art Unit 2114
/ASHISH THOMAS/Supervisory Patent Examiner, Art Unit 2114
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