DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-20 are currently pending in application 18/733,685.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheong et al. (US 2019/0304849 A1).
As per independent Claim 17, Cheong discloses a computer program product having a series of operating instructions stored on a non-transitory computer-readable medium that directs a data processing apparatus when executed thereby to perform operations to generate an output for a chip (See at least Figs. 1-3, Para 0012, Para 0029), the operations comprising:
receiving a set of chip quality characteristics for the chip during a testing phase of the chip, wherein the testing phase occurs before a time when the chip is transported to a customer (See Para 0013-0014); aligning each chip quality characteristic in the set of chip quality characteristics with characteristic data of a chip quality model, wherein the chip quality model is a machine learning model (See at least Para 0018, Para 0027-0028, Para 0030-0042);
generating the output of the chip quality model using the set of chip quality characteristics and respective aligned characteristic data, wherein the chip quality model uses parametric parameters from earlier tests as additional chip quality characteristics (See at least Para 0027, “The prediction process 300 obtains current WAT, CP, CP re-bin and FT data from the production run in step 302, then feeds the data into the trained model object in step 304. Feature engineering is performed in step 306, and a prediction is made in step 308.”; and communicating the output, wherein the output indicates a chip group parameter for the chip and indicates a system-level test (SLT) parameter for the chip, where the chip group parameter recommends a chip group (Bin) (See at least Para 0019, Para 0028, Para 0060-0061 and Para 0063-0067).
As per Claim 18, Cheong discloses wherein the machine learning model is a deep learning neural network (See at least Para 0021).
As per Claim 19, Cheong discloses wherein the operations are performed on a chip testing system or a cloud environment (See at least Figs. 1-3, Para 0012, Para 0029).
As per Claim 20, Cheong discloses validating the output using training data; and updating the chip quality model using results from the validating (See at least Para 0035-0050).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-16 are rejected under 35 U.S.C. 103(a) as being unpatentable over Cheong et al. (US 2019/0304849 A1) in view of Barbour et al. (US 2003/0120445 A1).
As per independent Claim 1, Cheong discloses a method (See at least Figs. 1-3, Para 0012), comprising:
receiving a set of chip quality characteristics for a chip during a testing phase of the chip, wherein the testing phase occurs before a time when the chip is transported to a customer; aligning each chip quality characteristic in the set of chip quality characteristics with characteristic data of a chip quality model, wherein the chip quality model is a machine learning model (See at least Para 0027, “The prediction process 300 obtains current WAT, CP, CP re-bin and FT data from the production run in step 302, then feeds the data into the trained model object in step 304. Feature engineering is performed in step 306, and a prediction is made in step 308.”; See also Para 0028, Para 0030-0042);
generating an output of the chip quality model using the set of chip quality characteristics and respective characteristic data that is aligned, wherein the chip quality model uses a weighting of at least one chip quality characteristic to modify the at least one chip quality characteristic (See at least Para 0053); and communicating the output, wherein the output indicates a chip group parameter for the chip and indicates a system-level test (SLT) parameter for the chip, where the chip group parameter recommends a chip group (See at least Para 0028, “The trained model can output a wafer-map with recommendations (plus optionally a confidence score) for chips to be sent to specified test step (usually burn-in) or to be shipped without specified test. The output, in the form of recommendations, can be provided in various formats, such as CSV files, or ingested directly into customer database systems.”; See also Para 0060-0061 and Para 0063-0067).
Cheong fails to expressly disclose wherein the chip quality characteristics include a repair history of the chip.
However, Barbour discloses a system/method wherein chip quality characteristics include a repair history of the chip (See Para 0051, “Memory integrated circuits often feature redundancy that can be invoked to do a `repair` of a faulty area of the chip. Such redundancy is used to increase the total number of yielding devices on a wafer. A mathematical model of the reliability of a particular chip is expected to be directly proportional to the number of killer defects the die possesses (and therefore repairs). Chips that are `perfect` and require no repair will have the best reliability. As the number of repairs/defects increases, the reliability of the part decreases. An illustration of this is shown in FIG. 2.”), and Barbour further discloses the chip quality model uses a weighting of at least one chip quality characteristic to modify the at least one chip quality characteristic (See at least Para 0053, “A number of possible sort indicators from chips during wafer test that may best predict whether another die will pass or fail. These possible indicators are then used as inputs to a common statistical inference technique (such as multiple linear regression or partial least squares) to make an empirical correlation between whether a die yields or not. The yield of immediately neighboring die is most influential on the die in question, while the yield of the same position on other wafers in the same lot also has some influence. The weight of these factors derive a score, which determines likelihood of yielding, called the statistical predicted yield ("SPY").”)
Therefore, before the effective filing date of the claimed invention, it would have been obvious for one of ordinary skill in the art to have included wherein the chip quality characteristics include a repair history of the chip, and the chip quality model uses a weighting of at least one chip quality characteristic to modify the at least one chip quality characteristic, as disclosed by Barbour in the system disclosed by Cheong, for the advantage of providing a method of chip quality optimization, with the ability to increase efficiency and effectiveness of the method by incorporating a variety of parameter (chip quality characteristic) data types used in the chip quality model for chip group recommendation and an SLT recommendation (See KSR [127 S Ct. at 1739] “The combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results.”).
Furthermore, the claimed chip quality model parameters/ metrics (chip quality characteristics) are design choices that are known in semiconductor activity; and to modify Cheong in view of Barbour to incorporate any of a wide variety of chip quality model parameters/ metrics (i.e. yield, defect density, parametric electrical limits, redundancy analysis (RA) data, laser fuse/eFuse data, post-repair data, and neighborhood data) would have been obvious to one of ordinary skill in the art to produce a desired result.
As per Claim 2, Cheong discloses wherein the set of chip quality characteristics include one or more of a type of chip, a manufacturer parameter, an environment parameter, or a chip location parameter (See at least Para 0027, Para 0031-0033).
As per Claim 3, Cheong discloses wherein the chip is an integrated circuit (IC) or a system on a chip (SoC) (See at least Para 0003).
As per Claim 4, Cheong discloses wherein the output is communicated to a validator system, further comprising: validating the chip group parameter and the SLT parameter using training data; and updating the chip quality model with results of the validating (See at least Para 0035-0050).
As per Claim 5, Cheong discloses wherein the output is communicated to a system or a process that directs the chip, after a chip probing combined (CPC) test, to a final test (FT) without system-level testing when the SLT parameter indicates that system-level testing is to be bypassed (See at least Para 0028).
As per Claim 6, Cheong discloses wherein the method executes prior to a CPC test and the method executes during a transit time of the chip (See also Para 0060-0061 and Para 0063-0067).
As per Claim 7, Cheong discloses wherein the output further includes training chip quality characteristics and is utilized to update the chip quality model (See at least Para 0035-0050).
As per Claim 8, Cheong discloses wherein the aligning each chip quality characteristic further utilizes a set of training labels representing respective chip quality characteristics to improve results of the chip quality model (See at least Para 0031, Para 0035-0050).
As per Claim 9, Cheong discloses wherein the set of chip quality characteristics is preprocessed to remove outlier data elements and to normalize parameters representing chip quality characteristics within the set of chip quality characteristics (See at least Para 0040-0044).
As per Claim 10, Cheong discloses herein user inputs are utilized to modify the set of chip quality characteristics (See at least Para 0031-0033, Para 0035-0050).
As per independent Claim 11, Cheong discloses a system, comprising:
a receiver, operational to receive a set of chip quality characteristics for a chip during a testing phase of the chip; and a chip quality evaluator, implemented on one or more processors, and operational to align each chip quality characteristic in the set of chip quality characteristics with characteristic data of a chip quality model (See at least Para 0027-0028, Para 0030-0042),
generating an output from the chip quality model using the set of chip quality characteristics and respective characteristic data that is aligned, and communicate the output, wherein the output indicates a chip group parameter for the chip and the output indicates a system-level test (SLT) parameter for the chip, where the chip group parameter recommends a chip group (See at least Para 0028, Para 0060-0061 and Para 0063-0067).
Cheong fails to expressly disclose wherein the chip quality characteristics include at least one neighbor chip parameter, and the chip quality model uses a minimum threshold probability for at least one chip quality characteristic.
However, Barbour discloses a system/method wherein chip quality characteristics include at least one neighbor chip parameter, and the chip quality model uses a minimum threshold probability for at least one chip quality characteristic (See at least Fig.7 and Para 0104, “Attention is directed to FIG. 7 which represents the flow of the local region yield analysis. The local region yield method involves using wafer test data 10 which is sorted by chip and computing the count of failures of the neighboring chips 12 surrounding a given die on a wafer. If the nearest eight dies are considered, for example, each die will therefore be classified into one of eight categories (0 bad neighbors, 1 bad neighbors, etc. up to 8 bad neighbors). Depending on the amount of clustering of defects on a wafer and the average number of `killer` (as opposed to `latent`, or reliability) defects on a wafer, the die in each bin will have a different probability of possessing a reliability defect. Die with 0 bad neighbors will have the lowest probability of having a reliability defect, while die with 8 bad neighbors will have the greatest probability of reliability failure.”
Therefore, before the effective filing date of the claimed invention, it would have been obvious for one of ordinary skill in the art to have included wherein the chip quality characteristics include at least one neighbor chip parameter, and the chip quality model uses a minimum threshold probability for at least one chip quality characteristic, as disclosed by Barbour in the system disclosed by Cheong, for the advantage of providing a method of chip quality optimization, with the ability to increase efficiency and effectiveness of the method by incorporating a variety of parameter (chip quality characteristic) data types used in the chip quality model for chip group recommendation and an SLT recommendation (See KSR [127 S Ct. at 1739] “The combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results.”).
Furthermore, the claimed chip quality model parameters/ metrics (chip quality characteristics) are design choices that are known in semiconductor manufacturing/ testing activity; and to modify Cheong in view of Barbour to incorporate any of a wide variety of chip quality model parameters/ metrics (i.e. yield, defect density, parametric electrical limits, redundancy analysis (RA) data, laser fuse/ eFuse data, post-repair data, and neighborhood data) would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to produce a desired result.
As per Claim 12, Cheong discloses a machine learning system, operational to communicate with the chip quality evaluator and to execute the chip quality model using the set of chip quality characteristics to generate the output (See at least Para 0023-0026, ML Training).
As per Claim 13, Cheong discloses a training system, operational to utilize the output to update the chip quality model to improve an accuracy of the output (See at least Para 0035-0050).
As per Claim 14, Cheong discloses a validator system, operational to utilize the output to validate the output against the chip quality model (See at least Para 0035-0050).
As per Claim 15, Cheong discloses wherein the receiver is further operational to receive user input parameters, wherein the user input parameters include a weighting for each of the chip quality characteristics (See at least Para 0052-0053).
As per Claim 16, Cheong discloses a transceiver, operational to communicate the output to a chip sorter system or a chip testing processing system (See at least Para 0028).
Response to Arguments
Applicant's arguments filed on 9/9/2026, with respect to Claims 1-16, have been considered but are moot in view of the new ground(s) of rejection.
Applicant's arguments filed on 9/9/2026, with respect to Claims 17-20, have been considered but are not persuasive. The claimed limitations are found in the prior art as stated/mapped in the rejection above. The rejection will remain as FINAL, based on the rejection above.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The Applicant’s arguments are addressed in the rejection above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure can be found in the PTO-892 Notice of References Cited. The Examiner suggests the applicant review all of these documents before submitting any amendments, especially the following:
Chen et al. (H. H. Chen and P. Shih, "Upstream data analytics to optimize system test," 2016 China Semiconductor Technology International Conference (CSTIC), Shanghai, China, 2016, pp. 1-4, doi: 10.1109/CSTIC.2016.7464073.) - See at least Figs.1-2 and Pgs. 2-3, Wafer-Level At-Risk Dies, “Studies have shown that passing dies surrounded closely by many failing dies (so-called good die in bad neighborhoods or GDBN) will show higher failure rates when subjected to reliability burn-in test [3]. We apply the same GDBN correlation to identify at-risk dies that must run SLT. On a wafer, consider the eight neighboring positions around a die in the center as shown in Fig. 1. A non-edge die is one where all eight positions are occupied by other dies; otherwise it’s defined as an edge die. A non-edge pass die is deemed to be at-risk when the number of failing neighbors exceeds a specified threshold. For an edge die, the at-risk threshold is adjusted to be lower. For any product, the at-risk thresholds need to be experimentally obtained over a large number of samples. The threshold is also a function of the product’s SLT DPPM goal. An example is provided here for a 28-nm smartphone SoC product with a sample size of 150 wafers and 300K dies. The dies are first divided into four bins where bins 1, 2 and 3 contain non-edge dies with failing neighbors in the ranges of 0~2, 3~4, and 5~8 respectively. All edge dies are placed in bin 4. The plot in Fig. 2 shows FT yield and SLT DPPM results for all four bins. Note that SLT DPPM numbers have been normalized by a number which cannot be provided due to confidentiality. But we can state that the normalized SLT DPPM goal for this product is ~3. From bin 1 to bin 4, one can observe the monotonic drop of FT yield and a corresponding rise of SLT DPPM. The rate of change is particularly sharp between bin 2 and bin 3. For this particular product, ~93% of the dies are contained in bins 1 and 2. Since they have acceptable SLT DPPM levels, SLT can be skipped and the at-risk threshold number is set at 4 failing neighbors. Note that all edge dies ended up as at-risk and show the worst SLT failure rate. If the SLT DPPM goal is lowered, the at-risk threshold number will also track lower, reaching zero at some point. This is where the GDBN scheme runs out of steam as no additional information is available to drive DPPM even lower among dies that can bypass SLT. The next scheme can address this limitation.”)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONATHAN P OUELLETTE whose telephone number is (571)272-6807. The examiner can normally be reached on M-F 8am-6pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynda C Jasmin, can be reached at telephone number (571) 272-6782. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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October 4, 2026
/JONATHAN P OUELLETTE/Primary Examiner, Art Unit 3629
