Prosecution Insights
Last updated: July 17, 2026
Application No. 18/733,746

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

Final Rejection §102§103
Filed
Jun 04, 2024
Priority
Nov 30, 2020 — nonprovisional of PCTCN2020132793 +1 more
Examiner
SENGDARA, VONGSAVANH
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Innoscience (Suzhou) Semiconductor Co. Ltd.
OA Round
2 (Final)
72%
Grant Probability
Favorable
3-4
OA Rounds
1y 1m
Est. Remaining
90%
With Interview

Examiner Intelligence

Grants 72% — above average
72%
Career Allowance Rate
669 granted / 931 resolved
+3.9% vs TC avg
Strong +19% interview lift
Without
With
+18.6%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
62 currently pending
Career history
1009
Total Applications
across all art units

Statute-Specific Performance

§101
1.3%
-38.7% vs TC avg
§103
83.7%
+43.7% vs TC avg
§102
12.2%
-27.8% vs TC avg
§112
2.1%
-37.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 931 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant's arguments filed on 06/25/2026 have been fully considered but they are not persuasive. Using BRI, Endoh discloses that amended claims. See rejection below. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1 and 3-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Endoh et al. 20070267655. PNG media_image1.png 451 751 media_image1.png Greyscale Regarding claim 1, figs. 2-10 of Endoh discloses a method for fabricating a semiconductor device, comprising: PNG media_image2.png 192 487 media_image2.png Greyscale providing a semiconductor stack comprising a substrate 10/10A, a first nitride semiconductor layer 11 (par [0056] - undoped GaN) on the substrate, and a second nitride semiconductor layer 12 (par [0056 - 12 made of undoped or n-type impurity doped AlGaN) on the first nitride semiconductor layer, wherein the second nitride semiconductor layer (AlGaN) having a bandgap greater than that of the first nitride semiconductor layer (GaN); PNG media_image3.png 280 524 media_image3.png Greyscale forming a first contact (21/22 – fig. 4) on the first nitride semiconductor layer; PNG media_image4.png 516 733 media_image4.png Greyscale forming a spacer 14 (figs. 4 and 9) attached to a sidewall of the first contact; forming a passivation layer 15 (inherent passivation layer – par [0057] upper protective film 15 made of SiN) on the spacer; and PNG media_image5.png 518 749 media_image5.png Greyscale forming a second contact 23 after the spacer is formed; wherein the spacer 14 is separated from the second contact 23 by the passivation layer 15 (fig. 10). Regarding claim 3, par [0064] of Endoh discloses further comprising performing annealing prior to the spacer is formed. Regarding claim 4, fig. 9 of Endoh discloses wherein the passivation layer has a convex surface (see the shape end tip). Regarding claim 5, fig. 10 of Endoh discloses further comprising defining a void 14C by the first contact and the spacer. Regarding claim 6, fig. 10 of Endoh discloses further comprising defining a void 14C between the sidewall of the first contact and a surface of the spacer. Regarding claim 7, fig. 10 of Endoh discloses wherein the sidewall of the first contact has a rougher surface than a surface of the spacer (see thickness of contact is thicker than that of spacer and thickness difference between the two represent different roughness from bottom to top surface). Regarding claim 8, fig. 10 of Endoh discloses wherein a surface of the spacer 14 adjacent to the sidewall of the first contact has a smoother surface than the sidewall of the first contact (since sidewall of 14 is smaller than sidewall of first contact which makes it smoother since comparing smaller surface to larger surface – smaller surface overall has less roughness than bigger surface means smoother). Regarding claim 9, fig. 10 of Endoh discloses further comprising defining a void by the first contact, the spacer and the passivation layer. Regarding claim 10, fig. 10 of Endoh discloses wherein the sidewall of the first contact has a rougher surface than a surface of the spacer (since first contact has larger surface area therefore overall surface roughness is rougher compare to smaller surface of spacer), and a surface of the passivation layer has a smoother surface (since first contact has larger surface area therefore overall surface roughness is rougher compare to smaller surface of passivation) than the sidewall of the first contact. Regarding claim 11, fig. 10 of Endoh discloses wherein the void is enclosed by the sidewall of the first contact and a surface of the spacer adjacent to the sidewall of the first contact. Regarding claim 12, par [0064] of Endoh discloses wherein the first contact is ohmic contact. Regarding claim 14, fig. 10 of Endoh discloses wherein the first contact is enclosed by the first nitride semiconductor layer, the second nitride semiconductor layer, the spacer, and the passivation layer. Regarding claim 13, figs. 2-10 of Endoh discloses a method for fabricating a semiconductor device, comprising: PNG media_image2.png 192 487 media_image2.png Greyscale providing a semiconductor stack comprising a substrate 10/10A, a first nitride semiconductor layer 11 (par [0056] - undoped GaN) on the substrate, and a second nitride semiconductor layer 12 (par [0056 - 12 made of undoped or n-type impurity doped AlGaN) on the first nitride semiconductor layer, wherein the second nitride semiconductor layer (AlGaN) having a bandgap greater than that of the first nitride semiconductor layer (GaN); PNG media_image3.png 280 524 media_image3.png Greyscale forming a first contact (21/22 – fig. 4) on the first nitride semiconductor layer; PNG media_image4.png 516 733 media_image4.png Greyscale forming a spacer 17 fig. 9 attached to a sidewall of the first contact (coplanar surface showing sidewall are coplanar which – attached to a sidewall of the first contact as claimed); forming a passivation layer 15 (inherent passivation layer – par [0057] upper protective film 15 made of SiN) on the spacer; and PNG media_image5.png 518 749 media_image5.png Greyscale forming a second contact 23 after the spacer is formed; wherein the spacer 17 is separated from the second contact 23 by the passivation layer 15 (fig. 10); wherein the spacer 17 covers both sidewalls of the first contact and extends to a top surface of the first contact. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 2 is rejected under 35 U.S.C. 103 as being unpatentable over Endoh in view of Tadjer et al. 20170338332. Regarding claim 2, Endoh discloses claim 1. Endoh do not disclose further comprising performing annealing after the spacer is formed. However, par [0044] of Tadjer disclose that SiN barrier layer is densified by annealing. As such, it would have been obvious to form a method Endoh further comprising performing annealing after the spacer is formed such as taught by Tadjer to densify the spacer and the passivation layer above the spacer the layer. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to VONGSAVANH SENGDARA whose telephone number is (571)270-5770. The examiner can normally be reached 9AM-6PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, PURVIS A. Sue can be reached at (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /VONGSAVANH SENGDARA/ Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Jun 04, 2024
Application Filed
Apr 20, 2026
Non-Final Rejection mailed — §102, §103
Jun 25, 2026
Response Filed
Jul 09, 2026
Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
72%
Grant Probability
90%
With Interview (+18.6%)
3y 3m (~1y 1m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 931 resolved cases by this examiner. Grant probability derived from career allowance rate.

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