DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I and Species 2 (fig. 5) directed to claims 1, 4-20, 30, 33-37 and 40-41 in the reply filed on 7/28/2026 is acknowledged.
Claims 2-3, 21-32 and 38-39 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected subject matter
Claim Rejections – 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4-11, 13, 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Byun et al. (US PG. Pub. 2002/0104874)
Regarding claim 1 – Byun teaches a printed circuit board (figs. 4-6, rotate figure 6 180 degrees) comprising: an insulating layer (120 [paragraph 0026] Byun states, “substrate 120”); a wiring layer (wiring layer including elements 124 & 170b) disposed on the insulating layer (120) and including a plurality of pads (124 [paragraph 0027] Byun states, “ball pad 124”) and at least one pattern (170 [paragraph 0029] Byun states, “enhanced pads 170”); and a solder resist layer (122 [paragraph 0027] Byun states, “solder resist (PSR) layer 122”) disposed on an upper portion of the insulating layer (120), covering at least a portion of the wiring layer ([paragraph 0027] Byun states, “Ball pads 124 are formed on the bottom surface of the substrate 120 and correspond to the metal wirings of the substrate 120”; the wirings connected to the pads/ pattern will be covered by the solder resist layer 122), and having a plurality of first openings (see opening of solder resist layer 122 exposing the pads 124) respectively exposing at least a portion of each of the plurality of pads (124) and one or more second openings (see opening of solder resist layer 122 exposing the pattern 170) respectively exposing at least a portion of the at least one pattern (170), wherein the one or more second openings respectively have at least two concave portions concave in a plane toward an inside of each of the second openings (figure 5 shows patterns 170b and 170c showing the dumbbell claimed shape with two concave portions that narrow the second opening in its middle section), and the plurality of first openings (opening exposing the pads 124) and the one or more second openings (opening exposing the pattern 170) are disposed in a mounting area of a semiconductor chip (200) of the solder resist layer (122; figure 4 & 6 show the first and second openings overlapping with the semiconductor chip 200).
Byun fails to explicitly teach wherein the pad and the pattern are made of a metal.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form the pad and the pattern of a metal material, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. Metal is known to be highly conductive and will reduce the electrical resistance when bonded to a mating component.
Regarding claim 4 – Byun teaches the printed circuit board of claim 1, wherein the second openings (fig. 5, see openings of 170b and 170c) respectively have a shape in which at least two openings (right and left circular openings) are spaced apart from each other on the plane and are connected by a groove of a straight shape (see dumbbell shape as shown in figure 7b).
Regarding claim 6 – Byun teaches the printed circuit board of claim 4, wherein each of the second openings (fig. 5, see openings of 170c and 170c) has a substantially dumbbell shape in the plane (figures 5 and 7b show the required “dumbbell shape”).
Regarding claim 7 – Byun teaches the printed circuit board of claim 1, wherein the plurality of first openings (fig. 5, see openings at pads 124) respectively have one opening (the first openings show a single circular opening and appear to have only “one opening”).
Regarding claim 8 – Byun teaches the printed circuit board of claim 1, wherein the solder resist layer (figs. 4-6, 120) further has a plurality of third openings (see far right openings in solder resist layer 120 that exposes the far right pads 124) respectively exposing at least another portion of the at least one metal pattern (metal pattern that encompasses pads 124 and wiring pattern 170), wherein the plurality of third openings respectively have one opening (claimed structure shown in figures 4-6).
Regarding claim 9 – Byun teaches the printed circuit board of claim 8, wherein the mounting area of the semiconductor chip (figs. 4-6, 200) includes a quadrangular area (see rectangular area shown in figures 4 & 5) created by substantially connecting, with a straight line, outer edges of outermost openings among openings including the plurality of first openings, the one or more second openings, and the plurality of third openings (figure 5 shows a top/plan view wherein when the outermost openings are connected in the horizontal and vertical directions create a rectangular structure as claimed).
Regarding claim 10 – Byun teaches the printed circuit board of claim 1, wherein the plurality of first openings (fig. 5, openings exposing the metal pads 124) are disposed at a central portion of the mounting area of the semiconductor chip (200), and the one or more second openings (openings exposing the metal pattern 170) are disposed in a peripheral portion surrounding the central portion of the mounting area of the semiconductor chip (200; claimed structure shown in figures 4-6).
Regarding claim 11 – Byun teaches the printed circuit board of claim 1, wherein at least one of the plurality of metal pads (fig. 5, 124) is spaced apart from the at least one metal pattern (170) and is continuously surrounded on an entire side by the at least one metal pattern (170; figure 5 shows the metal pattern 170 “surrounding” the entire side of the pad 124).
Regarding claim 13 – Byun teaches the printed circuit board of claim 1, wherein the plurality of first openings (fig. 5, openings exposing pads 124) are of a Solder Mask Defined (SMD) type (layer 122 is a “photo solder resist (PSR) layer and is considered a SMD type) and expose portions of the plurality of metal pads (124), respectively, and the one or more second openings (openings exposing pattern 170) are of a Solder Mask Defined (SMD) type (layer 122 is a “photo solder resist (PSR) layer and is considered a SMD type) and respectively expose at least a portion of the at least one metal pattern (170).
Regarding claim 19 – Byun teaches the printed circuit board of claim 1, wherein the second openings (fig. 5, openings exposing the pattern 170) respectively have a shape in which a first opening (lower inner opening of 170a shown in figure 5) having a first center point and a second opening (upper or left most opening of 170a) having a second center point are connected to each other on the plane, and in at least one of the one or more second openings (see opening structure shown in figure 170a), a virtual line connecting the first and second center points is substantially parallel or substantially perpendicular to a virtual edge of the mounting area of the semiconductor chip (200; figure 5 shows an “L” shape for the second opening and will meet both the parallel and perpendicular claimed structure).
Regarding claim 20 – Byun teaches the printed circuit board of claim 1, wherein the second openings (fig. 5, openings exposing the pattern 170) have a shape in which a first opening (right opening of 170c) having a first center point and a second opening (left opening of 170c) having a second center point are connected to each other on a plane (connected in a horizontal plane of figure 5), and in at least one second opening of the one or more second openings, a virtual line connecting the first and second center points (horizontal virtual line extending through 170c) is substantially parallel or substantially perpendicular to a virtual line (center point of fig. 5) connecting a center point of the mounting area of the semiconductor chip (200) and a center point of the at least one second opening (figures 4-5 show that the center virtual line extending vertically will pass through the horizontal virtual line extending through 170c and would appear to meet the claimed structure).
Regarding claim 30 – Byun teaches a printed circuit board (figs. 4-6, rotate figure 6 180 degrees) comprising: an insulating layer (120 [paragraph 0026] Byun states, “substrate 120”); a wiring layer (wiring layer including elements 124 & 170b) disposed on the insulating layer (120) and including a plurality of pads (124 [paragraph 0027] Byun states, “ball pad 124”) and a pattern (170 [paragraph 0029] Byun states, “enhanced pads 170”); a solder resist layer (122 [paragraph 0027] Byun states, “solder resist (PSR) layer 122”) disposed on an upper portion of the insulating layer (120), covering at least a portion of the wiring layer ([paragraph 0027] Byun states, “Ball pads 124 are formed on the bottom surface of the substrate 120 and correspond to the metal wirings of the substrate 120”; the wirings connected to the pads/ pattern will be covered by the solder resist layer 122), and having a plurality of first openings (see opening of solder resist layer 122 exposing the pads 124) respectively exposing at least a portion of each of the plurality of pads (124) and two openings (fig. 7c, see two openings to expose 174) respectively exposing at least a portion of the pattern (170), wherein the two openings are connected to each other and have at least two concave portions concave in a plane toward an inside of the two openings (claimed dumbbell structure shown in figure 5 and 7c); a plurality of first solder bumps (fig. 6, 160 [paragraph 0038] Byun states, “solder balls 160, 162”) respectively disposed on the plurality of first openings and respectively connected to the plurality of pads (124); and a second solder bump (180b) disposed on the two openings and connected to the pattern (170; claimed structure shown in figures 4-6).
Byun fails to explicitly teach wherein the pad and the pattern are made of a metal.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form the pad and the pattern of a metal material, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. Metal is known to be highly conductive and will reduce the electrical resistance when bonded to a mating component.
Regarding claim 33 – Byun teaches the printed circuit board of claim 30, wherein the two openings are connected by a groove having a width smaller than a diameter of the two openings (figures 5 and 7c show the dumbbell shaped structure claimed).
Regarding claim 34 – Byun teaches the printed circuit board of claim 33, wherein the two openings have a substantially dumbbell shape in the plane (figures 5 and 7c show the dumbbell shaped structure claimed).
Regarding claim 35 – Byun teaches the printed circuit board of claim 30, wherein at least one of the plurality of metal pads (fig. 5, 124) is spaced apart from the metal pattern (170) and is surrounded by the metal pattern (170) on the plane (figure 5 shows the metal pattern 170 “surrounding” the entire side of the pad 124 which is on the horizontal plane that connects the two openings).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Byun et al. in view of Kim et al. (US PG. Pub. 2012/0091584).
Regarding claim 5 – Byun teaches the printed circuit board of claim 4, but fails to explicitly teach wherein a length of the groove is smaller than a maximum radius of each of the openings.
Kim teaches a printed circuit board (figs. 7, 13 & 15) with a solder resist layer (400 [paragraph 0080] Kim states, “insulation layer pattern 400”) with openings and a groove (see openings having metal pattern 211/212/213 therein as shown in figures 13 and 15) wherein a length (fig. 7, L) of the groove (213) is smaller than a maximum radius (W1/2 = Maximum radius) of each of the openings (211/212 [paragraph 0084] Kim states, “a length L of the connection part 213 has a range of 1/10.times.W1 to 5.times.W1”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the printed circuit board having the groove and openings with dumbbell shape in the solder resist layer as taught by Byun with the groove being smaller than a maximum radius of each of the openings as taught by Kim because Kim states regarding these particular contacts, “because defective rates of a semiconductor package and a stacked semiconductor package with a flip chip structure using bumps decrease, the manufacturing yield can be increased” [paragraph 0130].
Claim(s) 14-18 & 36 is/are rejected under 35 U.S.C. 103 as being unpatentable over Byun et al. in view of Inoue et al. (US PG. Pub. 2013/0180772).
Regarding claim 14 – Byun teaches the printed circuit board of claim 1, but fails to teach further comprising: a first surface treatment layer disposed within the plurality of first openings and covering at least portions of respective exposed surfaces of the plurality of metal pads; and a second surface treatment layer disposed within the one or more second openings and covering at least a portion of an exposed surface of the at least one metal pattern.
Inoue teaches a printed circuit board (figs. 1-3) further comprising: a first surface treatment layer (fig. 3, 27 [paragraph 0060] Inoue states, “The coating layers 27 and 28 are configured of a nickel layer, a palladium layer and gold layer”) disposed within the plurality of first openings (31 [paragraph 0064] Inoue states, “opening portions 31”) and covering at least portions of respective exposed surfaces of the plurality of metal pads (11 [paragraph 0064] Inoue states, “pads 11”); and a second surface treatment layer (28) disposed within the one or more second openings (32) and covering at least a portion of an exposed surface of the at least one metal pattern (12/22).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the printed circuit board having the metal pads and metal pattens exposed through a solder resist as taught by Byun with the surface treatment layers (metals of nickel and gold) being applied to the metal pads and the metal patterns as taught by Inoue because nickel is commonly used as an adhesive layer to bond a gold layer thereon. Gold is desirable for it high conductivity and oxidation resistance.
Regarding claim 15 – Byun in view of Inoue teach the printed circuit board of claim 14, wherein the wiring layer (Inoue; fig. 3, wiring layer including pad 11 and pattern 12) includes a copper layer ([paragraph 0058] Inoue states, “pads 11 and 12 are formed mainly of copper which is a conductive material”), the first surface treatment layer (27) includes at least one of a nickel layer, a palladium layer, and a gold layer [paragraph 0060] Inoue states, “The coating layers 27 and 28 are configured of a nickel layer, a palladium layer and gold layer”), and the second surface treatment layer (28) includes at least one of the nickel layer, the palladium layer, and the gold layer (discussed in quoted paragraph 0060 above).
Regarding claim 16 – Byun in view of Inoue teach the printed circuit board of claim 14, further comprising: a plurality of first solder bumps (Inoue; fig. 1, 61[paragraph 0065] Inoue states, “first solder bump 61…second solder bump 62”) respectively disposed on the plurality of first openings (31) and respectively connected to the plurality of metal pads (11) through the first surface treatment layer (27); and one or more second solder bumps (62) respectively disposed on the one or more second openings (32) and respectively connected to the at least one metal pattern (12) through the second surface treatment layer (28).
Regarding claim 17 – Byun in view of Inoue teach the printed circuit board of claim 16, further comprising a semiconductor chip (Inoue; fig. 1, 131 [paragraph 0065] Inoue states, “IC chip 131”) disposed on the mounting area of the semiconductor chip (131) and connected to the plurality of first solder bumps (61) and the one or more second solder bumps (62).
Regarding claim 18 – Byun teaches the printed circuit board of claim 1, but fails to teach wherein the printed circuit board includes a plurality of insulating layers, a plurality of wiring layers respectively disposed on or in the plurality of insulating layers, and a plurality of via layers respectively penetrating at least one of the plurality of insulating layers and respectively connected to at least one of the plurality of wiring layers, the insulating layer is an insulating layer disposed on an outermost layer among the plurality of insulating layers, and the wiring layer is a wiring layer disposed on an outermost layer among the plurality of wiring layers.
Inoue teaches a printed circuit board (figs. 1-3, 101 [paragraph 0067] Inoue states, “wiring board 101”) wherein the printed circuit board (101) includes a plurality of insulating layers (see layers 30, 41, 42, 43, 44 & 45), a plurality of wiring layers (51 [paragraph 0070] Inoue states, “conductor layers 51”) respectively disposed on or in the plurality of insulating layers (claimed structure shown in figure 1), and a plurality of via layers (147 [paragraph 0071] Inoue states, “via conductors 147”) respectively penetrating at least one of the plurality of insulating layers (41-44) and respectively connected to at least one of the plurality of wiring layers (51), the insulating layer (30 [paragraph 0073] Inoue states, “solder resist 30”) is an insulating layer disposed on an outermost layer among the plurality of insulating layers, and the wiring layer (wiring layer including pad 11 and pattern 12) is a wiring layer disposed on an outermost layer among the plurality of wiring layers (claimed structure shown in figure 1).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the printed circuit board as taught by Byun with a plurality of insulating layers, plurality of wiring layers and a plurality of via layers connecting to the wiring layers as taught by Inoue because a multilayer structure allows increased circuit density allowing for a more efficient electrical device.
Regarding claim 36 – Byun teaches the printed circuit board of claim 30, but fails to teach further comprising: a first surface treatment layer disposed within the plurality of first openings and covering at least portions of respective exposed surfaces of the plurality of metal pads; and a second surface treatment layer disposed within the two openings and covering at least a portion of an exposed surface of the metal pattern, wherein the plurality of first solder bumps are respectively connected to the plurality of metal pads through the first surface treatment layer, and the second solder bump is connected to the metal pattern through the second surface treatment layer.
Inoue teaches a printed circuit board (figs. 1-3, 101) further comprising: a first surface treatment layer (fig. 3, 27 [paragraph 0060] Inoue states, “The coating layers 27 and 28 are configured of a nickel layer, a palladium layer and gold layer”) disposed within the plurality of first openings (31 [paragraph 0064] Inoue states, “opening portions 31”) and covering at least portions of respective exposed surfaces of the plurality of metal pads (11 [paragraph 0064] Inoue states, “pads 11”); and a second surface treatment layer (28) disposed within the two openings (32) and covering at least a portion of an exposed surface of the metal pattern (12/22), wherein the plurality of first solder bumps (fig. 1, 61 & 62 [paragraph 0065] Inoue states, “first solder bump 61…second solder bump 62”) are respectively connected to the plurality of metal pads (11) through the first surface treatment layer (27), and the second solder bump (62) is connected to the metal pattern (12) through the second surface treatment layer (28).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the printed circuit board having the metal pads and metal pattens exposed through a solder resist as taught by Byun with the surface treatment layers (metals of nickel and gold) being applied to the metal pads and the metal patterns as taught by Inoue because nickel is commonly used as an adhesive layer to bond a gold layer thereon. Gold is desirable for it high conductivity and oxidation resistance.
Allowable Subject Matter
Claims 37 & 40-41 are allowed.
Claim 12 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ishizaki (US PG. Pub. 2024/0314929) discloses a semiconductor storage device.
Shibutani (US PG. Pub. 2014/0376202) discloses a PCB.
Hattori (US PG. Pub. 2014/0353026) discloses a wiring board.
Pearson et al. (US PG. Pub. 2005/0211750) discloses solder bar connections on electronic packages
Hirose et al. (US PG. Pub. 2003/0102151) discloses a multilayer build-up wiring board.
Harada (US PG. Pub. 2003/0025201) discloses an IC chip mounted to a wiring board.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN T SAWYER whose telephone number is (571)270-5469. The examiner can normally be reached M-F 8:30 am - 5pm.
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/STEVEN T SAWYER/Primary Examiner, Art Unit 2847
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